# US 2017/0256557 A1 · Metal-ono-vacuum tube charge trap flash (vtctf) nonvolatile memory and the method for making the same

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- Number: US 2017/0256557 A1
- Document ID: US20170256557A1
- Status: Published application
- Kind: A1
- Application number: 15/202,418
- Filed: 2016-07-05
- Published: 2017-09-07
- Earliest claimed: 2016-03-03
- Assignees: Zing Semiconductor Corporation
- Applicants: Zing Semiconductor Corporation
- Inventors: DEYUAN XIAO
- Web page: https://patentgrep.com/patent/US20170256557A1

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/691: {having more than two programming levels}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ONO) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current due to adoption ONO as the gate dielectric layer.

## Claims

### Claim 1

A method of forming a vacuum tube nonvolatile memory, comprising the steps of:
providing a substrate;
sequentially forming a dielectric layer, a source layer, a second dielectric layer, a gate layer and a hard mask layer on said substrate;
patterning said second dielectric layer, said gate layer and said hard mask layer to form a gate structure;
trimming said second dielectric layer, said gate layer of said gate structure to make the width of said second dielectric layer and said gate layer smaller than the width of said hard mask layer;
forming a gate dielectric layer on said substrate, and performing etching to form gate dielectric layer sidewalls;
forming a drain layer; and
forming an interlayer dielectric layer and performing planarization to from a vacuum channel.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising annealing said source layer and said drain layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein said annealing is performed in the environment of He, N2, Ar or H2.

### Claim 4 (depends on 2)

The method according to claim 2, wherein said annealing is performed in the temperature range of 600˜1000° C.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the pressure in said vacuum channel is in the range of 0.1 torr˜50 torr.

### Claim 6 (depends on 1)

The method according to claim 1, wherein said source layer and said drain layer are the metal materials selected from the group consisting of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond and the combination of these materials.

### Claim 7 (depends on 1)

The method according to claim 1, wherein said gate layer is the metal materials comprising Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, TiN, TaN, or the combination of these materials.

### Claim 8 (depends on 1)

The method according to claim 1, wherein said gate dielectric layer is the metal materials comprising oxide, oxynitride, silicon nitride, Al2O3, AlN and HfO.

### Claim 9 (depends on 1)

The method according to claim 1, wherein said hard mask layer is the metal materials comprising oxynitride, silicon nitride, and TiN.

### Claim 10

A vacuum tube nonvolatile memory, comprising:
a substrate;
a first dielectric layer and a source layer on said substrate;
a gate structure on said source layer, wherein said gate structure comprises a gate layer and a hard mask layer, a gate dielectric layer located on sidewalls of said gate structure, and a vacuum channel, wherein the width of said second dielectric layer and said gate layer smaller than the width of said hard mask layer; and
a drain layer on said gate structure and seal said vacuum channel.

### Claim 11 (depends on 10)

The vacuum tuber nonvolatile memory according to claim 10, wherein said source layer and said drain layer are the metal materials selected from the group consisting of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond and the combination of these materials.

### Claim 12 (depends on 10)

The vacuum tube nonvolatile memory according to claim 10, wherein said gate layer is the metal materials comprising Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, TiN, TaN, or the combination of these materials.

### Claim 13 (depends on 10)

The vacuum tuber nonvolatile memory according to claim 10, wherein said dielectric layer is the metal materials comprising oxide, oxynitride, silicon nitride, Al2O3, AlN and HfO.

### Claim 14 (depends on 10)

The vacuum tube nonvolatile memory according to claim 10, wherein said hard mask layer is the metal materials comprising oxynitride, silicon nitride, and TiN.