# US 2017/0256552 A1 · Application of Antiferroelectric Like Materials in Non-Volatile Memory Devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256552 A1 - Document ID: US20170256552A1 - Status: Published application - Kind: A1 - Application number: 15/057,884 - Filed: 2016-03-01 - Published: 2017-09-07 - Earliest claimed: 2016-03-01 - Assignees: NaMLab gGmbH - Applicants: NaMLab gGmbH - Inventors: Uwe SCHRÖDER; Milan PESIC - Web page: https://patentgrep.com/patent/US20170256552A1 ## CPC - H10B 53/30: characterised by the memory core region - G11C 11/1659: {Cell access} - G11C 11/221: {using ferroelectric capacitors} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 11/2275: {Writing or programming circuits or methods} - G11C 11/24: using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) - G11C 11/5657: {using ferroelectric storage elements} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - H10B 51/30: characterised by the memory core region - H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers} - H10D 30/0415: {of FETs having ferroelectric gate insulators} - H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs} - H10D 64/689: {having ferroelectric layers} - G11C 2213/15: Current-voltage curve - G11C 2213/79: Array wherein the access device being a transistor - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced ferroelectrics (FFE), anti-ferroelectric (AFE) and relaxor type ferroelectric (RFE) materials. Each integrated device includes a material stack with a PHL material layer disposed between two electrodes. Application of this material is dependent on inducing of an electric field bias over the stack. According to one option, electrodes having different workfunction values can be employed to induce the required built-in bias field and enable use of PHL materials. According to another option, a PHL material and charges, e.g., a charge interlayer, are disposed between two electrodes such that an induced built-in bias field appears. Integrated devices employing the PHL material stack include memories, transistors, and piezo- and pyroelectric devices. ## Claims ### Claim 1 An integrated circuit element, comprising: a first electrode; a second electrode; and a layer disposed between the first and second electrodes and comprising a pinched hysteresis loop (PHL) material having a charge-voltage characteristic with two hysteresis loops, the storage layer having an internal bias field that shifts the charge-voltage characteristic of the PHL material to align one of the two hysteresis loops with a zero voltage state such that the PHL material is capable of being maintained in a selected polarization state in the absence of an external electric field. ### Claim 2 (depends on 1) The integrated circuit element of claim 1, wherein the first and second electrodes have different compositions resulting in a workfunction value difference between the first and second electrodes, the workfunction value difference inducing the internal bias field. ### Claim 3 (depends on 2) The integrated circuit element of claim 2, wherein the first and second electrodes have a workfunction value difference in the range of 0.7 to 1.5 eV. ### Claim 4 (depends on 1) The integrated circuit element of claim 1, wherein the layer further comprises fixed electrical charges that induce the internal bias field. ### Claim 5 (depends on 1) The integrated circuit element of claim 1, wherein the layer further comprises at least one interlayer disposed between the first and second electrodes. ### Claim 6 (depends on 5) The integrated circuit element of claim 5, wherein the at least one interlayer comprises fixed electrical charges that induce the internal bias field. ### Claim 7 (depends on 5) The integrated circuit element of claim 5, wherein the at least one interlayer comprises a material with a high crystallization temperature or a high band gap. ### Claim 8 (depends on 5) The integrated circuit element of claim 5, wherein the at least one interlayer comprises Al2O3, SrO, or another rare earth oxide. ### Claim 9 (depends on 1) The integrated circuit element of claim 1, wherein the PHL material comprises a field induced ferroelectric (FFE) material. ### Claim 10 (depends on 9) The integrated circuit element of claim 9, wherein the FFE material comprises ZrO2 or ZraXbO2, where X is an element of the periodic table, and a>0, b>0. ### Claim 11 (depends on 9) The integrated circuit element of claim 9, wherein the FFE material comprises ZrO2 or ZraXbO2, wherein X is one of Hf, Si, Al, Ge, and elements of the second group of the periodic table, and a>0, b>0. ### Claim 12 (depends on 9) The integrated circuit element of claim 9, wherein the FFE material comprises HfaXbO2, wherein X is an element of the periodic table and a>0, b>0. ### Claim 13 (depends on 9) The integrated circuit element of claim 9, wherein the FFE material comprises HfaXbO2, wherein X is an element of the periodic table with smaller ionic radius than Hf and a>0, b>0. ### Claim 14 (depends on 9) The integrated circuit element of claim 9, wherein the FFE material comprises HfaXbO2, wherein X is one of Zr, Si, Al, Ge, and elements of the second group of the periodic table and a>0, b>0. ### Claim 15 (depends on 1) The integrated circuit element of claim 1, wherein the PHL material comprises an anti-ferroelectric (AFE) material. ### Claim 16 (depends on 1) The integrated circuit element of claim 1, wherein the PHL material comprises a relaxor type (RFE) material. ### Claim 17 (depends on 1) The integrated circuit element of claim 1, wherein the first and second electrodes comprise one or more of the following: Ti, TiN, TiSi, TiAlN, TaN, TaCN, TaSi, W, WSi, WN, Al, Ru, RuO, RuO2, Re, Pt, Ir, IrO, IrO2, In2O3, InSnO, SnO, ZnO, Ti, Ni, NiSi, Nb, Ga, GaN, C, Ge, Si, doped Si, SiC and GeSi. ### Claim 18 (depends on 1) The integrated circuit element of claim 1, wherein the layer has a thickness in the range of 1 and 20 nm. ### Claim 19 (depends on 1) The integrated circuit element of claim 1, wherein the integrated circuit element is a capacitor structure. ### Claim 20 (depends on 1) The integrated circuit element of claim 1, wherein the first electrode is a substrate. ### Claim 21 (depends on 1) The integrated circuit element of claim 1, wherein the integrated circuit element is a transistor structure. ### Claim 22 (depends on 1) The integrated circuit element of claim 1, wherein the integrated circuit element is a storage device. ### Claim 23 (depends on 1) The integrated circuit element of claim 1, wherein the integrated circuit element is a piezoelectric device or a pyroelectric device. ### Claim 24 (depends on 1) The integrated circuit element of claim 1, wherein the layer is a dielectric layer. ### Claim 25 An integrated circuit element, comprising: a first electrode having a first workfunction value; a second electrode having a second workfunction value that is different from the first workfunction value of the first electrode; and a layer disposed between the first and second electrode, the layer comprising a pinched hysteresis loop (PHL) material whose charge-voltage characteristic is shifted by an internal bias field generated by a difference between the first and second workfunction values.