# US 2017/0256531 A1 · Soi integrated circuit equipped with a device for protecting against electrostatic discharges

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0256531 A1
- Document ID: US20170256531A1
- Status: Published application
- Kind: A1
- Application number: 15/591,565
- Filed: 2017-05-10
- Published: 2017-09-07
- Earliest claimed: 2013-08-05
- Assignees: Commissariat à I'Énergie Atomique et aux Énergies Alternatives; STMcroelectronics S.A.; Centre National De La Recherche Scientifique
- Applicants: Commissariat à I'énergie atomique et aux énergies alternatives; STMcroelectronics SA; Centre National de la Recherche Scientifique
- Inventors: Yohann Solaro; Sorin Cristoloveanu; Claire Fenouillet-Beranger; Pascal Fonteneau
- Web page: https://patentgrep.com/patent/US20170256531A1

## CPC

- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 18/251: {Lateral thyristors}
- H10D 18/40: with turn-on by field effect
- H10D 18/80: Bidirectional devices, e.g. triacs
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/192: {Base regions of thyristors}
- H10D 64/291: {Gate electrodes for thyristors}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

## Claims

### Claim at position 1

1-34. (canceled)

### Claim 35

A manufacture comprising an integrated circuit comprising a protection device for protection of said integrated circuit against electrostatic discharge, said protection comprising, first and second electrodes, a buried insulant layer, a first bipolar transistor, a second bipolar transistor, and a first semiconductor ground plane, wherein said buried insulant layer has a thickness that is no greater than fifty nanometers, wherein said first and second bipolar transistors are arranged on said buried insulant layer, wherein one of said first and second bipolar transistors is an NPN transistor, wherein another of said first and second bipolar transistors is a PNP transistor, wherein a base of said first bipolar transistor merges with a collector of said second bipolar transistor, wherein a base of said second bipolar transistor merges with a collector of said first bipolar transistor, wherein said first and second bipolar transistors are configured for selectively conducting a discharge current between said first and second electrodes, wherein said first semiconductor ground plane is arranged under said buried insulant layer, wherein said first semiconductor ground plane is capable of being electrically biased, wherein said first semiconductor ground plane extends underneath said base of said first bipolar transistor, wherein said first semiconductor ground plane has a first type of doping, wherein said base of said first bipolar transistor has said first type of doping, and wherein said first semiconductor ground plane has a dopant density that is at least ten times greater than a dopant density of said base of said first bipolar transistor.

### Claim 36 (depends on 35)

The manufacture of claim 35, wherein a dopant density in said base of said first bipolar transistor is no greater than 1018 cm−3.

### Claim 37 (depends on 35)

The manufacture of claim 35, further comprising a semiconductor layer, wherein said first and second bipolar transistors are formed in said semiconductor layer, and wherein said semiconductor layer is no greater that fifteen nanometers in thickness.

### Claim 38 (depends on 35)

The manufacture of claim 35, further comprising a second semiconductor ground plane, wherein said second semiconductor group plane lies under said buried insulant layer, wherein said second semiconductor ground plane is configured to be electrically biased, wherein said second semiconductor ground plane has a second type of doping, wherein said second semiconductor ground plane extends underneath said base of said second bipolar transistor, and wherein said first type of doping differs from said second types of doping.

### Claim 39 (depends on 38)

The manufacture of claim 38, wherein said first semiconductor ground plane contacts said second semiconductor ground plane.

### Claim 40 (depends on 39)

The manufacture of claim 39, wherein there exists a first projection and a second projection, wherein said first projection is a projection of a third semiconductor ground plane onto said buried insulant layer, wherein said second projection is a projection of a third base onto said buried insulant layer, wherein said first projection is larger than said second projection, wherein said first projection comprises said second projection, wherein said third semiconductor ground plane is selected from the group consisting of said first semiconductor ground plane and said second semiconductor ground plane, and wherein said third base is selected from the group consisting of said first base and said second base.

### Claim 41 (depends on 39)

The manufacture of claim 39, wherein there exists a first projection and a second projection, wherein said first projection is a projection of a third semiconductor ground plane onto said buried insulant layer, wherein said second projection is a projection of a third base onto said buried insulant layer, wherein said third semiconductor ground plane is selected from the group consisting of said first semiconductor ground plane and said second semiconductor ground plane, and wherein said third base is selected from the group consisting of said first base and said second base, and wherein at least a portion of said second projection is above said first projection.

### Claim 42 (depends on 39)

The manufacture of claim 39, wherein respective projections of said first and second ground planes on said buried insulant layer include respective projections of said bases of the first and second bipolar transistors on said buried insulant layer.

### Claim 43 (depends on 38)

The manufacture of claim 38, further comprising an electrically insulating element and a junction, wherein said junction is between said base of said first bipolar transistor and said base of said second bipolar transistor, wherein said electrically insulating element separates said first and second semiconductor ground planes, and wherein said electrically insulating element is underneath said junction.

### Claim 44 (depends on 41)

The manufacture of claim 41, further comprising a semiconductor substrate, wherein said electrically insulating element comprises another buried insulant layer, and wherein said another buried insulant layer is between said semiconductor substrate and said first and second semiconductor ground planes.

### Claim 45 (depends on 35)

The manufacture of claim 35, wherein one of said first and second electrodes contacts said base of said second bipolar transistor.

### Claim 46 (depends on 35)

The manufacture of claim 35, wherein neither electrode contacts said base of said first bipolar transistor has no electrode.

### Claim 47 (depends on 35)

The manufacture of claim 35, further comprising a first upper face, a second upper face, a third upper face, and a fourth upper face, wherein said first upper face is an upper face of said base of said first bipolar transistor, wherein said second upper face is an upper face of said second bipolar transistor, wherein said third upper face is an upper face of an emitter of said first bipolar transistor, wherein said fourth upper face is an upper face of an emitter of said second bipolar transistor, and wherein said first upper face, said second upper face, said third upper face, and said fourth upper face are flush with each other.

### Claim 48

A method comprising fabricating an integrated circuit, wherein fabricating said integrated circuit comprises forming a first semiconductor ground plane by implanting a first type of dopant into a semiconductor substrate that is arranged under a buried insulant layer, said buried insulant layer having a thickness less than or equal to 50 nm, forming first and second bipolar transistors on said buried insulant layer, wherein one of said first and second transistors is an NPN transistor and an other of said first and second transistors is a PNP transistor, wherein a base of said first transistor has said first type of dopant, wherein said base of said first transistor and a base of said second transistor merge with respective collectors of said second and first bipolar transistors, wherein said base of said first bipolar transistor is formed underneath said first semiconductor ground plane, wherein doping of said base of said first transistor is performed during implantation of said first type of dopant for formation of said first semiconductor ground plane, wherein a dopant density upon completion of said implantation in said first semiconductor ground plane is at least ten times greater than a dopant density of said base of said first bipolar transistor.

### Claim 49 (depends on 48)

The method of claim 48, further comprising forming an electrode that is electrically connected to said first semiconductor ground plane and interconnecting said electrode with a bias circuit.

### Claim 50 (depends on 48)

The method of claim 48, further comprising causing a dopant density in said base of said first transistor to be no greater than 1018 cm−3 after forming said interconnect with said bias circuit.

### Claim 51 (depends on 49)

The method of claim 49, wherein forming said electrode comprises forming said electrode such that said electrode is not in contact with said base of said first bipolar transistor.

### Claim 52 (depends on 48)

The method of claim 48, wherein forming first and second bipolar transistors on said buried insulant layer comprises forming said first and second bipolar transistors in a semiconductor layer that is arranged on said buried insulant layer and, after implantation to form said first semiconductor ground plane, executing plural implanting steps, each of which includes masking said base of said first bipolar transistor.