# US 2017/0256512 A1 · Methods and Apparatus of Packaging Semiconductor Devices

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- Number: US 2017/0256512 A1
- Document ID: US20170256512A1
- Status: Published application
- Kind: A1
- Application number: 15/601,801
- Filed: 2017-05-22
- Published: 2017-09-07
- Earliest claimed: 2011-11-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Wei Tu; Yian-Liang Kuo; Tsung-Fu Tsai; Ru-Ying Huang; Ming-Song Sheu; Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US20170256512A1

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/654: Top-view layouts
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
depositing a polymer layer at least partially over a redistribution layer over a substrate, the depositing the polymer layer forming a first surface facing away from the substrate at a first distance from the substrate and forming a second surface facing away from the substrate at a second distance from the substrate less than the first distance;
depositing an underbump metallization over both the first surface and the second surface, the underbump metallization extending through the first surface to make electrical contact with the redistribution layer; and
placing a bump in electrical connection with the underbump metallization, the underbump metallization being between the bump and the second surface.

### Claim 2 (depends on 1)

The method of claim 1, wherein after the depositing the underbump metallization the underbump metallization has a third surface facing the substrate that is located a third distance from the substrate less than the second distance.

### Claim 3 (depends on 2)

The method of claim 2, wherein the third surface has a width of between about 80 μm and about 270 μm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the polymer layer has a third surface opposite the second surface and wherein a distance between the third surface and the second surface is between about 5 μm and about 30 μm.

### Claim 5 (depends on 1)

The method of claim 1, wherein the bump has a third surface facing the substrate at a third distance from the substrate, the third distance being less than the first distance.

### Claim 6 (depends on 5)

The method of claim 5, wherein the underbump metallization extends through the second surface to make contact with a dielectric layer different from the polymer layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the redistribution layer has a first straight portion and a second curved portion.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
forming a redistribution layer over a substrate;
placing a passivation layer over the redistribution layer, wherein a first portion of the passivation layer is in physical contact with a top surface of the redistribution layer and a second portion of the passivation layer is in physical contact with a sidewall of the redistribution layer adjacent to the top surface of the redistribution layer;
forming a first opening through the first portion of the passivation layer;
depositing an underbump metallization through the first opening and over the second portion of the passivation layer; and
placing a conductive bump onto the underbump metallization, wherein after the placing the conductive bump the conductive bump is located over the second portion of the passivation layer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a second opening through the first portion of the passivation layer different from the first opening, wherein the depositing the underbump metallization deposits the underbump metallization through the second opening.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a third opening through the first portion of the passivation layer different from the first opening and the second opening, wherein the depositing the underbump metallization deposits the underbump metallization through the third opening.

### Claim 11 (depends on 8)

The method of claim 8, wherein the underbump metallization has a first longitudinal axis in a top down view, the first longitudinal axis being aligned with a second longitudinal axis of the redistribution layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the underbump metallization has a third longitudinal axis in a top down view, the third longitudinal axis being mis-aligned with the second longitudinal axis of the redistribution layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the underbump metallization has a fourth longitudinal axis in a top down view, the fourth longitudinal axis being mis-aligned with the second longitudinal axis of the redistribution layer.

### Claim 14 (depends on 8)

The method of claim 8, wherein the underbump metallization has a first longitudinal axis in a top down view, the first longitudinal axis being mis-aligned with a second longitudinal axis of the redistribution layer.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
placing a passivation layer over a redistribution layer and a substrate, the passivation layer comprising a first portion directly over the redistribution layer and a second portion laterally removed from being directly over the redistribution layer;
forming at least one opening through the passivation layer; and
placing an underbump metallization through the at least one opening to form a first interface between the underbump metallization and the redistribution layer, a second interface between the underbump metallization and the first portion of the passivation layer, and a third interface between the underbump metallization and the second portion of the passivation layer, wherein the third interface is closer to the substrate than the second interface.

### Claim 16 (depends on 15)

The method of claim 15, wherein the third interface is closer to the substrate than the first interface.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming the at least one opening through the passivation layer comprises forming an opening through the second portion of the passivation layer.

### Claim 18 (depends on 15)

The method of claim 15, further comprising placing a conductive bump directly over the third interface.

### Claim 19 (depends on 15)

The method of claim 15, wherein the second interface is continuous.

### Claim 20 (depends on 15)

The method of claim 15, wherein the second interface is discontinuous.