# US 2017/0256509 A1 · Method of Manufacturing Molded Semiconductor Packages Having an Optical Inspection Feature > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256509 A1 - Document ID: US20170256509A1 - Status: Published application - Kind: A1 - Application number: 15/059,827 - Filed: 2016-03-03 - Published: 2017-09-07 - Earliest claimed: 2016-03-03 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Swee Kah Lee; Hock Heng Chong; Mei Chin Ng; Aileen Manantan Soriano; Fong Mei Lum; Muhammad Muhammat Sanusi; Soon Lock Goh - Web page: https://patentgrep.com/patent/US20170256509A1 ## CPC - H10W 72/90: Bond pads, in general - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - H10W 70/411: {Chip-supporting parts, e.g. die pads} - H10W 70/421: {Shapes or dispositions} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/457: {of metallic layers on leadframes} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W 72/019: {of bond pads} - H10W 72/01971: {Cleaning, e.g. oxide removal} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads are also embedded in the mold compound and electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described. ## Claims ### Claim 1 A method of manufacturing molded semiconductor packages, the method comprising: providing a molded semiconductor substrate comprising a mold compound in which semiconductor dies and metal pads are embedded, each metal pad being electrically connected to one of the semiconductor dies and uncovered by the mold compound at a first main surface of the mold compound; singulating the molded semiconductor substrate into individual molded packages each of which comprises one or more of the semiconductor dies and the corresponding metal pads, each metal pad having a bottom face uncovered by the mold compound at the first main surface, the metal pads disposed around a periphery of each molded package also having a side face uncovered by the mold compound at an edge along which the molded packages were singulated; immersing the molded packages in a chemical bath which roughens the bottom face of each metal pad and removes burrs from the side face of the metal pads disposed around the periphery of each molded package; and plating the faces of the metal pads uncovered by the mold compound after immersing the molded packages in the chemical bath. ### Claim 2 (depends on 1) The method of claim 1, wherein the chemical bath is selected from the group consisting of: a hydrogen peroxide solution; a ferric chloride solution; a salt solution; copper sulfate; and ferric sulfate. ### Claim 3 (depends on 1) The method of claim 1, wherein the chemical bath comprises sodium persulfate. ### Claim 4 (depends on 1) The method of claim 1, wherein the faces of the metal pads uncovered by the mold compound are plated by electroless plating. ### Claim 5 (depends on 4) The method of claim 4, wherein the electroless plating comprises an electroless nickel immersion gold (ENIG) process in which a layer of nickel-phosphorus or nickel-boron alloy is deposited on the faces of the metal pads uncovered by the mold compound and then covered with a layer of gold. ### Claim 6 (depends on 5) The method of claim 5, further comprising: introducing a catalyst for the electroless plating prior to depositing the layer of nickel-phosphorus or nickel-boron alloy. ### Claim 7 (depends on 6) The method of claim 6, wherein the metal pads comprise copper, wherein the catalyst comprises palladium, and wherein the faces of the metal pads uncovered by the mold compound have a palladium-catalyzed copper surface prior to depositing the layer of nickel-phosphorus or nickel-boron alloy. ### Claim 8 (depends on 1) The method of claim 1, further comprising: cleaning the molded packages in an acidic solution before immersing the molded packages in the chemical bath; and rinsing the molded packages after cleaning the molded packages in the acidic solution and before immersing the molded packages in the chemical bath. ### Claim 9 (depends on 1) The method of claim 1, further comprising: covering the plated faces of the metal pads with a protective layer. ### Claim 10 (depends on 1) The method of claim 1, wherein between about 3 to 15 microns of metal is etched away from the faces of the metal pads uncovered by the mold compound while the molded packages are immersed in the chemical bath. ### Claim 11 (depends on 1) The method of claim 1, wherein the molded semiconductor substrate is temporarily fixed to a UV curable tape at least during the immersing and the plating, and wherein the UV curable tape has a heat resistance and a chemical resistance such that the UV curable tape can withstand the chemical bath. ### Claim 12 (depends on 1) The method of claim 1, wherein the molded semiconductor substrate is singulated into the individual molded packages using a single-step sawing process. ### Claim at position 13 13-20. (canceled) ### Claim 21 (depends on 11) The method of claim 11, wherein the UV curable tape remains intact after singulating the molded semiconductor substrate.