# US 2017/0256508 A1 · Semiconductor chip, semiconductor device and manufacturing process for manufacturing the same

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- Number: US 2017/0256508 A1
- Document ID: US20170256508A1
- Status: Published application
- Kind: A1
- Application number: 15/057,673
- Filed: 2016-03-01
- Published: 2017-09-07
- Earliest claimed: 2016-03-01
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Chun-Jun ZHUANG; Hung-Chun KUO; Chun-Chin HUANG
- Web page: https://patentgrep.com/patent/US20170256508A1

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/654: Top-view layouts
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads.

## Claims

### Claim 1

A semiconductor chip, comprising:
a chip main body;
at least one first pillar disposed adjacent to a surface of the chip main body, wherein the first pillar has a first profile from a bottom view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile; and
at least one second pillar disposed adjacent to the surface of the chip main body, wherein the second pillar has a second profile from a bottom view, and a shape of the first profile is different from a shape of the second profile.

### Claim 2 (depends on 1)

The semiconductor chip of claim 1, wherein the at least one first pillar is a plurality of first pillars arranged along the first direction.

### Claim 3 (depends on 1)

The semiconductor chip of claim 1, wherein the at least one second pillar is a plurality of second pillars arranged in an array.

### Claim 4 (depends on 1)

The semiconductor chip of claim 1, wherein an area of the first profile is substantially equal to an area of the second profile.

### Claim 5 (depends on 1)

The semiconductor chip of claim 1, wherein the second profile has a first width along the first direction and a second width along the second direction perpendicular to the first direction, and the first width of the second profile is substantially equal to the second width of the second profile.

### Claim 6 (depends on 5)

The semiconductor chip of claim 5, wherein the first width of the first profile is about two times the first width of the second profile, and the second width of the first profile is about half of the second width of the second profile.

### Claim 7

A semiconductor device, comprising:
a substrate main body;
a plurality of first bump pads disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile; and
a redistribution layer disposed adjacent to the surface of the substrate main body, wherein the redistribution layer includes a first portion disposed between two first bump pads.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising a chip bonding area on the substrate main body and an electrical element outside the chip bonding area, the first portion of the redistribution layer is disposed within the chip bonding area, and the first portion of the redistribution layer is physically connected to the electrical element outside the chip bonding area.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein a virtual perimeter around an outermost ring of a group of the first bump pads outlines the chip bonding area.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the first portion of the redistribution layer extends through the chip bonding area.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the chip bonding area is a first chip bonding area, the semiconductor device further comprising a second chip bonding area on the substrate main body, and wherein the electrical element is a bonding pad, a second portion of the redistribution layer, or a bump pad in the second chip bonding area, and the electrical element and the redistribution layer are in a same layer.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, further comprising a plurality of bumps disposed on the first bump pads.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein the first bump pads are arranged along the first direction, and the first portion of the redistribution layer is parallel with the first direction.

### Claim 14 (depends on 7)

The semiconductor device of claim 7, further comprising a plurality of second bump pads, each of the second bump pads has a second profile from a top view, and a shape of the second profile is different from a shape of the first profile, and an area of the first profile is substantially equal to an area of the second profile.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first width of the first profile is about two times a first width of the second profile, and the second width of the first profile is about half of a second width of the second profile.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further comprising a semiconductor chip bonded to the first bump pads, the second bump pads, or the first bump pads and the second bump pads.

### Claim 17 (depends on 7)

The semiconductor device of claim 7, further comprising a mother board and at least one interconnection element, wherein the interconnection element connects the mother board and the substrate main body.

### Claim at position 18

-20. (canceled)

### Claim 21

A semiconductor device, comprising:
a substrate main body having a surface, the substrate main body including a plurality of pads adjacent to the surface of the substrate main body; and
a plurality of first metal bumps having a first profile from a top view and a plurality of second metal bumps having a second profile from a top view disposed on the pads;
wherein the first profile of the first metal bumps is different from the second profile of the second metal bumps, and a cross-sectional area of each of the second metal bumps is substantially equal to a cross-sectional area of each of the first metal bumps.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, the first width of the first profile is greater than the second width of the first profile; and
wherein the second profile has a first width along the first direction and a second width along the second direction perpendicular to the first direction, and the first width of the second profile is substantially equal to the second width of the second profile.

### Claim 23 (depends on 21)

The semiconductor device of claim 21, further comprising:
a redistribution layer disposed adjacent to the surface of the substrate main body, wherein the redistribution layer includes a first portion passing through a gap space between two pads of the plurality of pads.