# US 2017/0256489 A1 · Soc with integrated voltage regulator using preformed mim capacitor wafer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256489 A1 - Document ID: US20170256489A1 - Status: Published application - Kind: A1 - Application number: 15/601,604 - Filed: 2017-05-22 - Published: 2017-09-07 - Earliest claimed: 2015-07-15 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Jun Zhai; Kunzhong Hu - Web page: https://patentgrep.com/patent/US20170256489A1 ## CPC - H10W 20/496: {Capacitor integral with wiring layers} - H10D 1/20: Inductors - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 20/43: Layouts of interconnections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/014: {using batch processing} - H10W 90/00: Package configurations - H10W 72/0198: {batch processes} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit. ## Claims ### Claim 1 An integrated circuit, comprising: a semiconductor die; a plurality of wiring layers, wherein at least one metal-insulator-metal (MIM) capacitor is formed within the plurality of wiring layers, and wherein the plurality of wiring layers further include conductors to couple the semiconductor die from a first surface of the plurality of wiring layers that abuts the semiconductor die to a second surface of the plurality of wiring layers that is opposite to the first surface; a circuit including at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die, the circuit arranged substantially below at least a portion of the MIM capacitor in the plurality of layers, wherein the circuit is electrically coupled to the capacitor through the plurality of wiring layers; and a plurality of electrical connectors to couple the integrated circuit to a circuit board, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the plurality of layers comprises assembling a first portion of the plurality of layers on a semiconductor wafer. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the plurality of layers comprises assembling a first portion of the plurality of layers on a semiconductor wafer, and wherein a second portion of the plurality of layers comprises a redistribution layer applied to MIM layers subsequent to removing the semiconductor wafer. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the capacitor is positioned proximate to a portion of the first set of electrical conductors electrically coupled to a power grid. ### Claim 5 (depends on 1) The integrated circuit of claim 1, further comprising a redistribution layer. ### Claim 6 (depends on 1) The integrated circuit of claim 1, further comprising a redistribution layer, wherein the redistribution layer comprises a third surface coupled to the second surface of the plurality of layers, and wherein the plurality of electrical connectors are coupled to a fourth surface at points separate from an area of the second surface that is occupied by the circuit. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein the redistribution layer electrically couples the plurality of layers and the plurality of electrical connectors. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the MIM capacitor comprises alternating layers of conductors and insulators. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein the MIM capacitor comprises alternating layers of conductors and insulators, and wherein the conductors comprise metal and/or conducting polymers. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the base comprises a silicon wafer. ### Claim 11 An integrated circuit, comprising: a semiconductor die; a plurality of wiring layers, wherein at least one metal-insulator-metal (MIM) capacitor is formed within the plurality of wiring layers, and wherein the plurality of wiring layers further include conductors to couple the semiconductor die from a first surface of the plurality of wiring layers that abuts the semiconductor die to a second surface of the plurality of wiring layers that is opposite to the first surface; a redistribution layer coupled to the plurality of wiring layers; a circuit including at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die, the circuit arranged substantially below at least a portion of the MIM capacitor in the plurality of layers, wherein the circuit is electrically coupled to the capacitor through the plurality of wiring layers; and a plurality of electrical connectors to couple the integrated circuit to a circuit board, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the plurality of layers comprises assembling a first portion of the plurality of layers on a semiconductor wafer. ### Claim 13 (depends on 11) The integrated circuit of claim 11, wherein the plurality of layers comprises assembling a first portion of the plurality of layers on a semiconductor wafer, and wherein a second portion of the plurality of layers comprises the redistribution layer applied to MIM layers subsequent to removing the semiconductor wafer. ### Claim 14 (depends on 11) The integrated circuit of claim 11, wherein the capacitor is positioned proximate to a portion of the first set of electrical conductors electrically coupled to a power grid. ### Claim 15 (depends on 11) The integrated circuit of claim 11, wherein the redistribution layer comprises a third surface coupled to the second surface of the plurality of layers, and wherein the plurality of electrical connectors are coupled to a fourth surface at points separate from an area of the second surface that is occupied by the circuit. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the redistribution layer electrically couples the plurality of layers and the plurality of electrical connectors. ### Claim 17 (depends on 11) The integrated circuit of claim 11, wherein the MIM capacitor comprises alternating layers of conductors and insulators. ### Claim 18 (depends on 11) The integrated circuit of claim 11, wherein the MIM capacitor comprises alternating layers of conductors and insulators, and wherein the conductors comprise metal and/or conducting polymers. ### Claim 19 (depends on 11) The integrated circuit of claim 11, wherein the base comprises a silicon wafer. ### Claim 20 (depends on 11) The integrated circuit of claim 11, wherein the redistribution layer electrically couples the MIM capacitor to the circuit.