# US 2017/0256408 A1 · Methods and structures to prevent sidewall defects during selective epitaxy > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256408 A1 - Document ID: US20170256408A1 - Status: Published application - Kind: A1 - Application number: 15/604,550 - Filed: 2017-05-24 - Published: 2017-09-07 - Earliest claimed: 2016-01-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Niloy MUKHERJEE; Niti GOEL; Sanaz K. GARDNER; Pragyansri PATHI; Matthew V. METZ; Sansaptak DASGUPTA; Seung Hoon SUNG; James M. POWERS; Gilbert DEWEY; Benjamin CHU-KUNG; Jack T. KAVALIEROS; Robert S. CHAU - Web page: https://patentgrep.com/patent/US20170256408A1 ## CPC - H10P 14/3822: {Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/405: {Orientations of crystalline planes} - H10D 62/82: Heterojunctions - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/853: {comprising FinFETs} - H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials} - H10P 14/271: {characterised by the preparation of substrate for selective deposition} - H10P 14/2905: {Silicon, silicon germanium or germanium} - H10P 14/3258: {Crystal orientation} - H10P 14/3411: {Silicon, silicon germanium or germanium} - H10P 14/3414: {being group IIIA-VIA materials} - H10P 14/3466: {Crystal orientation} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 84/0167: {Manufacturing their channels} - H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in. ## Claims ### Claim 1 An integrated circuit structure, comprising: a first isolation structure on a substrate, the first isolation structure having an upper portion on a lower portion, the lower portion having a substantially flat surface having a width, and the upper portion having a width on the lower portion less than the width of the substantially flat surface of the lower portion providing exposed portions of the substantially flat surface of the lower portion; and a second isolation structure on the substrate, the second isolation structure having an upper portion on a lower portion, the lower portion having a substantially flat surface having a width, and the upper portion having a width on the lower portion less than the width of the substantially flat surface of the lower portion providing exposed portions of the substantially flat surface of the lower portion; and an epitaxial semiconductor material laterally directly between the upper portion of the first isolation structure and the upper portion of the second isolation structure, the epitaxial semiconductor material on a portion of the exposed portions of the substantially flat surfaces of the lower portions of the first and second isolation structures, the epitaxial semiconductor material comprising a fin. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein the substrate is a monocrystalline silicon substrate. ### Claim 3 (depends on 2) The integrated circuit structure of claim 2, wherein the epitaxial semiconductor material is a group III-V material layer. ### Claim 4 (depends on 2) The integrated circuit structure of claim 2, wherein the epitaxial semiconductor material is a germanium material layer. ### Claim 5 (depends on 1) The integrated circuit structure of claim 1, further comprising: a first seam between the upper portion and lower portion of the first isolation structure; and a second seam between the upper portion and lower portion of the second isolation structure. ### Claim 6 (depends on 1) The integrated circuit structure of claim 1, further comprising: a second epitaxial semiconductor material below the epitaxial semiconductor material, the second epitaxial semiconductor material laterally between the upper portion of the first isolation structure and the upper portion of the second isolation structure, the second epitaxial semiconductor material on a second portion of the exposed portions of the substantially flat surfaces of the lower portions of the first and second isolation structures, the second epitaxial semiconductor material comprising a pyramidal top surface, wherein the epitaxial semiconductor material is on the pyramidal top surface of the second epitaxial semiconductor material. ### Claim 7 (depends on 6) The integrated circuit structure of claim 6, further comprising: a third epitaxial semiconductor material below the second epitaxial semiconductor material, the third epitaxial semiconductor material laterally between the lower portion of the first isolation structure and the lower portion of the second isolation structure, the third epitaxial semiconductor material, the third epitaxial semiconductor material comprising a pyramidal top surface above the substantially flat surfaces of the lower portions of the first and second isolation structures, wherein the second epitaxial semiconductor material is on the pyramidal top surface of the third epitaxial semiconductor material. ### Claim 8 (depends on 7) The integrated circuit structure of claim 7, further comprising: a fourth epitaxial semiconductor material below the third epitaxial semiconductor material, the fourth epitaxial semiconductor material laterally between the lower portion of the first isolation structure and the lower portion of the second isolation structure, the third epitaxial semiconductor material, the third epitaxial semiconductor material comprising a pyramidal top surface, wherein the third epitaxial semiconductor material is on the pyramidal top surface of the fourth epitaxial semiconductor material. ### Claim 9 (depends on 8) The integrated circuit structure of claim 8, wherein the fourth epitaxial semiconductor material is on the substrate, and wherein a portion of the third epitaxial semiconductor material is on the substrate. ### Claim 10 (depends on 1) The integrated circuit structure of claim 1, wherein the lower portions of the first and second isolation structures comprises substantially vertical sidewalls. ### Claim 11 A method of fabricating an integrated circuit structure, the method comprising: forming a first isolation structure on a substrate, the first isolation structure having an upper portion on a lower portion, the lower portion having a substantially flat surface having a width, and the upper portion having a width on the lower portion less than the width of the substantially flat surface of the lower portion providing exposed portions of the substantially flat surface of the lower portion; and forming a second isolation structure on the substrate, the second isolation structure having an upper portion on a lower portion, the lower portion having a substantially flat surface having a width, and the upper portion having a width on the lower portion less than the width of the substantially flat surface of the lower portion providing exposed portions of the substantially flat surface of the lower portion; and forming an epitaxial semiconductor material laterally directly between the upper portion of the first isolation structure and the upper portion of the second isolation structure, the epitaxial semiconductor material on a portion of the exposed portions of the substantially flat surfaces of the lower portions of the first and second isolation structures, the epitaxial semiconductor material comprising a fin. ### Claim 12 (depends on 11) The method of claim 11, wherein the substrate is a monocrystalline silicon substrate. ### Claim 13 (depends on 12) The method of claim 12, wherein the epitaxial semiconductor material is a group III-V material layer. ### Claim 14 (depends on 12) The method of claim 12, wherein the epitaxial semiconductor material is a germanium material layer. ### Claim 15 (depends on 11) The method of claim 11, wherein the lower portions of the first and second isolation structures comprises substantially vertical sidewalls. ### Claim 16 A method to form a trench for growing a selective epitaxial buffer material, the method comprising: forming first and second shallow trench isolation (STI) regions on a substrate surface, the first and second STI regions having first and second STI inner sidewalls defining first and second lower trench sidewalls of a trench having a bottom surface that is the substrate surface; the first and second lower trench sidewalls forming an inward angle of 55 degrees with respect to the substrate surface; and selectively epitaxially growing a layer of crystal epitaxial material from the substrate surface and in the trench. ### Claim 17 (depends on 16) The method of claim 16, wherein the layer of crystal epitaxial material has (111) crystal index material sidewalls touching the first and second STI inner sidewalls. ### Claim 18 (depends on 16) The method of claim 16, wherein the layer of crystal epitaxial material is a layer of buffer material and further comprising: selectively epitaxially growing a device layer of device crystal epitaxial material from a top surface of the buffer material. ### Claim 19 A method to form a combined trench for growing a selective epitaxial buffer material, the method comprising: forming first and second shallow trench isolation (STI) regions on a substrate surface, the first and second STI regions having first and second STI inner sidewalls defining first and second lower trench sidewalls of a lower trench, the lower trench having a bottom surface that is the substrate surface, the lower trench having a lower trench upper opening; and forming third and fourth STI regions on the first and second STI regions, the third and fourth STI regions having third and fourth STI inner sidewalls defining third and fourth upper trench sidewalls of an upper trench, the upper trench exposing the lower trench upper opening and the substrate surface; the upper trench having an upper trench lower surface above and completely surrounding the lower trench upper opening. ### Claim 20 (depends on 19) The method of claim 19, wherein the upper trench has a height at least 1.5 times a width and at least 1.5 times a length of the upper trench; and wherein the third and fourth STI inner sidewalls are perpendicular to the substrate surface. ### Claim 21 (depends on 19) The method of claim 19, further comprising: selectively epitaxially growing a layer of crystal epitaxial material from the substrate surface, into the lower trench and into the upper trench; and wherein the layer of crystal epitaxial material is not grown from STI top surfaces of the lower trench. ### Claim 22 (depends on 21) The method of claim 21, wherein the layer of crystal epitaxial material is a layer of buffer material and further comprising: a layer of device crystal epitaxial material on a top surface of the buffer material, the device crystal epitaxial material selectively epitaxially grown from the top surface of the buffer material. ### Claim 23 (depends on 21) The method of claim 21, wherein the epitaxial material has (111) crystal index sidewalls touching the first and second STI inner sidewalls; and wherein the epitaxial material has (110)crystal index vertical sidewalls touching the third and fourth STI inner sidewalls. ### Claim 24 (depends on 19) The method of claim 19, wherein the first and second STI inner sidewalls form an inward angle of 55 degrees with respect to the substrate surface. ### Claim 25 (depends on 19) The method of claim 19, wherein the first and second STI inner sidewalls are perpendicular to the substrate surface.