# US 2017/0256318 A1 · Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate

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- Number: US 2017/0256318 A1
- Document ID: US20170256318A1
- Status: Published application
- Kind: A1
- Application number: 15/600,491
- Filed: 2017-05-19
- Published: 2017-09-07
- Earliest claimed: 2009-01-30
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Takatoshi MINAMOTO; Toshiki HISADA; Dai NAKAMURA
- Web page: https://patentgrep.com/patent/US20170256318A1

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/43: Layouts of interconnections
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

## Claims

### Claim 1

(cancelled)

### Claim 2

A semiconductor memory device, comprising:
a memory cell unit including a plurality of memory cells connected hi series, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a third word line connected to the third memory cell;
a fourth word line connected to the fourth memory cell;
a driver circuit configured to apply a voltage to the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell; and
a first transistor including a first diffused layer and a second diffused layer, wherein the first diffused layer is connected to the first word line, and the second diffused layer is connected to the driver circuit,
wherein when data is written into the first memory cell, a first voltage is applied to the first word line, a second voltage is applied to the second word line and the third word line, and a third voltage is applied to the fourth word line,
wherein the first voltage is larger than both the second voltage and the third voltage, and the third voltage is larger than the second voltage,
wherein the second memory cell and the third memory cell are located between the first memory cell and the fourth memory cell, and
wherein the second word line and the third word line are not located above the first diffused layer and the second diffused layer.

### Claim 3 (depends on 2)

The device according to claim 2, further comprising:
a second transistor connected between the second word line and the driver circuit;
a third transistor connected between the third word line and the driver circuit; and
a fourth transistor connected between the fourth word line and the driver circuit,
wherein each of the first word line, the second word line, the third word line, and the fourth word line is arranged in a first direction,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor has a gate length in a second direction perpendicular to the first direction, and
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged hi the first direction.

### Claim 4 (depends on 3)

The device according to claim 3,
wherein the first memory cell, the second memory cell, the third memory cell, and the fourth memory ceil are connected between a first selection transistor and a second selection transistor,
wherein the memory cell unit is connected to a bit line via the first selection transistor, and is connected to a source line via the second selection transistor, and
wherein a distance between the first transistor and the memory cell unit is smaller than a distance between the second transistor and the memory cell unit.

### Claim 5 (depends on 4)

The device according to claim 4, wherein the second memory cell, the third memory cell and the fourth memory cell are located between the first memory cell and the second selection transistor.

### Claim 6 (depends on 2)

The device according to claim 2, wherein the second voltage turns off the second memory cell and the third memory cell regardless of held data.

### Claim 7 (depends on 2)

The device according to claim 2, wherein the second voltage is a positive voltage.

### Claim 8 (depends on 6)

The device according to claim 6, wherein the second voltage is a positive voltage.

### Claim 9 (depends on 2)

The device according to claim 2, further comprising a contact plug formed on the second diffused layer,
wherein the first transistor is connected to the driver circuit via the contact plug, and
wherein the fourth word line is located in a region above the second diffused layer and between a gate electrode of the first transistor and the contact plug.

### Claim 10 (depends on 2)

The device according to claim 2, wherein the semiconductor memory device is a NAND memory device.