# US 2017/0256309 A1 · Nonvolatile memory device including page buffer and method of operating the nonvolatile memory device

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- Number: US 2017/0256309 A1
- Document ID: US20170256309A1
- Status: Published application
- Kind: A1
- Application number: 15/361,451
- Filed: 2016-11-27
- Published: 2017-09-07
- Earliest claimed: 2016-03-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: HYUN-JUN YOON
- Web page: https://patentgrep.com/patent/US20170256309A1

## CPC

- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C 2211/5643: Multilevel memory comprising cache storage devices
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile memory device including a page buffer and a method of operating the nonvolatile memory device, the method including performing a first sensing operation using a first sensing voltage; precharging some bit lines from among a plurality of bit lines, according to first data stored in a first latch unit of a page buffer due to the first sensing operation; resetting the first latch unit; and performing a second sensing operation using a second sensing voltage.

## Claims

### Claim 1

A method of operating a nonvolatile memory device, the method comprising:
performing a first sensing operation on memory cells of the nonvolatile memory device using a first sensing voltage;
precharging some bit lines from among a plurality of bit lines connected to the memory cells, according to first data stored in a first latch unit of a page buffer due to the first sensing operation;
resetting the first latch unit after said precharging; and
performing a second sensing operation on the memory cells using a second sensing voltage.

### Claim 2 (depends on 1)

The method of claim 1, further comprising storing second data sensed according to the second sensing operation in the first latch unit.

### Claim 3 (depends on 2)

The method of claim 2, further comprising transmitting the stored second data to an external controller as read data.

### Claim 4 (depends on 3)

The method of claim 3, wherein the nonvolatile memory device further comprises a second latch unit configured to transmit data to the external controller and to receive data from the external controller,
wherein the transmitting of the second data to the external controller as the read data comprises:
dumping the second data stored in the first latch unit to the second latch unit; and
transmitting the second data dumped to the second latch unit to the external controller.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
resetting the first latch unit to a first logic state before the first sensing operation; and
precharging all of the plurality of bit lines together according to the first logic state of the first latch unit before the first sensing operation.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first sensing operation is a coarse sensing operation using the first sensing voltage having a pre-read level, and the second sensing operation is a fine sensing operation using the second sensing voltage having a read level,
wherein the pre-read level is lower than the read level.

### Claim 7 (depends on 1)

The method of claim 1, wherein the memory cells of the nonvolatile memory device comprise multi-level memory cells, and the nonvolatile memory device performs a plurality of read operations in response to a read command received from an external controller,
wherein each of the plurality of read operations comprises at least the first and second sensing operations.

### Claim 8 (depends on 1)

The method of claim 1, wherein the page buffer further comprises a second latch unit, wherein while the first and second sensing operations are performed, data un-related to the first and second sensing operations is stored in the second latch unit.

### Claim 9 (depends on 8)

The method of claim 8, further comprising, before the performing of the first sensing operation, performing a first read operation comprising at least two sensing operations,
wherein while the first and second sensing operations are performed, data related to the first read operation is stored in the second latch unit.

### Claim 10 (depends on 1)

The method of claim 1, wherein the nonvolatile memory device comprises a switch unit configured to control electrical connection between at least one sensing node and the first latch unit,
wherein during the resetting of the first latch unit, the switch unit is turned off.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
precharging some bit lines from among the plurality of bit lines according to second data stored in the first latch unit due to the second sensing operation;
resetting the first latch unit after the precharging according to the second data; and
performing a third sensing operation using a third sensing voltage.

### Claim 12

A method of operating a nonvolatile memory device comprising a page buffer, the page buffer comprising a first latch unit connected to sensing nodes and a second latch unit electrically connected to the first latch unit, the method comprising:
storing a result of a first sensing operation performed on a plurality of memory cells in the first latch unit, in response to a read command;
selectively precharging some bit lines from among a plurality of bit lines connected to the plurality of memory cells according to a logic state of the first latch unit;
after the selectively precharging, setting the first latch unit to a first logic state without dumping the result of the first sensing operation stored in the first latch unit to the second latch unit; and
storing a result of a second sensing operation performed on at least some memory cells from among the plurality of memory cells in the first latch unit.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
setting the first latch unit to the first logic state in response to the read command before the first sensing operation; and
precharging the plurality of bit lines according to the set logic state of the first latch unit before the first sensing operation.

### Claim 14 (depends on 12)

The method of claim 12, wherein the setting of the first latch unit to the first logic state comprises setting the first latch unit to the first logic state by setting or resetting the first latch unit.

### Claim 15 (depends on 12)

The method of claim 12, wherein the first sensing operation is a coarse sensing operation using a first sensing voltage having a pre-read level, and the second sensing operation is a fine sensing operation using a second sensing voltage having a read level.

### Claim 16

A method of operating a nonvolatile memory device comprising:
setting a logic state of a first latch unit to a first logic state;
precharging all of a plurality of bit lines connected to the first latch unit according to the set logic state of the first latch unit;
after the precharging, performing a first sensing operation on memory cells connected to the plurality of bit lines using a first sensing voltage and storing a result of the first sensing operation as data in the first latch unit;
selectively precharging some of the plurality of bit lines according to a logic state of the data stored in the first latch unit;
after the selectively precharging, setting the logic state of the first latch unit to the first logic state; and
performing a second sensing operation on the memory cells using a second sensing voltage and storing a result of the second sensing operation in the first latch unit as final data.

### Claim 17 (depends on 17)

The method of claim 17, wherein the setting the logic state of the first latch unit after the selectively precharging is performed while the plurality of bit lines are disconnected from the first latch unit.

### Claim 18 (depends on 16)

The method of claim 16, further comprising outputting the final data stored in the first latch unit to an external controller.

### Claim 19 (depends on 16)

The method of claim 16, wherein the first sensing operation is a coarse sensing operation and the first sensing voltage comprises a pre-read voltage, and the second sensing operation is a fine sensing operation and the second sensing voltage comprises a read voltage that is greater than the pre-read voltage.

### Claim 20 (depends on 16)

The method of claim 16, wherein the nonvolatile memory device comprises a second latch unit, wherein data un-related to the first and second sensing operations is stored in the second latch unit while the first and second sensing operations are performed.