# US 2017/0256296 A1 · Digital perceptron

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- Number: US 2017/0256296 A1
- Document ID: US20170256296A1
- Status: Published application
- Kind: A1
- Application number: 15/059,733
- Filed: 2016-03-03
- Published: 2017-09-07
- Earliest claimed: 2016-03-03
- Assignees: Flashsilicon Incorporation
- Applicants: FlashSilicon Incorporation
- Inventors: Lee WANG
- Web page: https://patentgrep.com/patent/US20170256296A1

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G06F 12/10: Address translation
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence)
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C 15/04: using semiconductor elements
- G11C 15/046: {using non-volatile storage elements}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

## Claims

### Claim 1

A digital perceptron device, comprising:
a non-volatile content memory array having m rows by n columns of first memory cells for parallel comparing a n-bit input symbol with a number m of n-bit non-volatile content symbols pre-configured in the m rows of first memory cells respectively having m first output nodes, wherein each of the m first output nodes generates an indication signal indicative of whether the n-bit input symbol matches its pre-configured n-bit non-volatile content symbol;
a match detector circuit having m detector cells that are respectively connected to the m first output nodes and that have m second output nodes, wherein each of the m detector cells generates a digital switching signal at its second output node after receiving a corresponding indication signal;
a non-volatile perceptive memory array having m rows by q columns of second memory cells, wherein the m rows of second memory cells are respectively connected to the m second output nodes and pre-configured with a number m of q-bit non-volatile perceptive symbols, wherein a received digital switching signal with a first voltage level switches on a corresponding row of second memory cells to output a corresponding q-bit non-volatile perceptive symbol as a q-bit output symbol, wherein a received digital switching signal with a second voltage level switches off a corresponding row of second memory cells, and wherein m, n and q are greater than one;
wherein each of the m rows by n columns of first memory cells and the m rows by q columns of second memory cells comprises a non-volatile memory (NVM) device pair, and each NVM device pair outputs one of a high operating voltage VDD and a ground voltage VSS of the digital perceptron device in response to two input voltages VDD and VSS.

### Claim 2 (depends on 1)

The digital perceptron device according to claim 1, wherein the n-bit input symbol matches zero or one of the number m of pre-configured n-bit non-volatile content symbols so that zero or one of the number m of pre-configured q-bit non-volatile perceptive symbols is outputted as the q-bit output symbol.

### Claim 3 (depends on 1)

The digital perceptron device according to claim 1, wherein each of the m detector cells generates the digital switching signal in response to a first control signal, and wherein the first control signal is activated when the digital perceptron device is turned on.

### Claim 4 (depends on 3)

The digital perceptron device according to claim 3, further comprising:
an input bus for receiving a n-bit input signal; and
an input buffer and driver unit connected between bit lines of the non-volatile content memory array and the input bus for temporarily storing and amplifying the n-bit input signal to output the n-bit input symbol according to the first control signal.

### Claim 5 (depends on 3)

The digital perceptron device according to claim 3, further comprising:
an output bus; and
an output buffer and driver unit located between bit lines of the non-volatile perceptive memory array and the output bus for temporarily storing the q-bit output symbol and amplifying the q-bit output symbol signal to drive the output bus, wherein whether the output buffer and driver unit is electrically connected to the bit lines of the non-volatile perceptive memory array depends on the first control signal, and whether the output buffer and driver unit is electrically connected to the output bus depends on a second control signal; and
wherein the second control signal is activated when the n-bit input symbol matches one of the number m of pre-configured n-bit non-volatile content symbols.

### Claim 6 (depends on 1)

The digital perceptron device according to claim 1, wherein the m rows by n columns of first memory cells are organized in a plurality of NAND strings and the non-volatile content memory array comprises:
a number m of match lines respectively connected to the m first output node, each match line being formed by series-connected switching transistors of the first memory cells in a corresponding NAND string;
a number n of first complementary bit line pairs for receiving the n-bit input symbol, each first complementary bit line pair being connected to the first memory cells in a column; and
a common source line for connecting the same-side terminals of the match lines altogether to a predetermined voltage terminal.

### Claim 7 (depends on 6)

The digital perceptron device according to claim 6, wherein each first memory cell consists of:
a first non-volatile memory (NVM) device and a second NVM device, the first NVM device and the second NVM device respectively in a conducting state and a non-conducting state indicating a first non-volatile binary datum, the first NVM device and the second NVM device respectively in the non-conducting state and the conducting state indicating a second non-volatile binary datum; and
the switching transistor, wherein two first terminals of the first NVM device and the second NVM device are connected together to a gate electrode of the switching transistor, a second terminal of the first NVM device being connected to a first bit line of one first complementary bit line pair, a second terminal of the second NVM device being connected to a second bit line of the first complementary bit line pair.

### Claim 8 (depends on 1)

The digital perceptron device according to claim 1, wherein the non-volatile perceptive memory array comprises:
a number m of word lines respectively connected to the m second output node, each word line being formed by gates of access transistors of the second memory cells in a row;
a number q of second complementary bit line pairs, each second complementary bit line pair being connected to the second memory cells in a column; and
a number q of output bit lines, each of which extends vertically and is connected to the outputs of the second memory cells in a column.

### Claim 9 (depends on 8)

The digital perceptron device according to claim 8, wherein each second memory cells consists of:
a third NVM device and a fourth NVM device, the third NVM device and the fourth NVM device respectively in a conducting state and a non-conducting state indicating a third non-volatile binary datum, and the third NVM device and the fourth NVM device respectively in the non-conducting state and the conducting state indicating a fourth non-volatile binary datum; and
the access transistor, wherein two first terminals of the third NVM device and the fourth NVM device are connected together to a source electrode of the access transistor, a second terminal of the third NVM device being connected to a first bit line of one second complementary bit line pair, a second terminal of the second NVM device being connected to a second bit line of the second complementary bit line pair;
wherein drain electrodes of the access transistors in one column are connected together to form one of the output bit lines.

### Claim 10 (depends on 1)

The digital perceptron device according to claim 1, wherein the number m of pre-configured n-bit non-volatile content symbols in the non-volatile content memory array and the number m of pre-configured q-bit non-volatile perceptive symbols in the non-volatile perceptive memory array are capable of being re-configured in real time according to at least one of coding efficiency and a learning algorithm.

### Claim 11 (depends on 1)

The digital perceptron device according to claim 1, wherein the q-bit output symbol is autonomously processed with the n-bit input symbol according to the number m of pre-configured n-bit non-volatile content symbols and the number m of pre-configured q-bit non-volatile perceptive symbols.

### Claim 12

A method for operating a digital perceptron device comprising a non-volatile content memory array and a non-volatile perceptive memory array, the method comprising:
parallel comparing an n-bit input symbol with a number m of n-bit non-volatile content symbols pre-configured in the non-volatile content memory array having m rows by n columns of first memory cells so that each of the m rows of first memory cells generates an indication signal indicative of whether the n-bit input symbol matches its pre-configured n-bit non-volatile content symbol;
respectively obtaining m digital switching signals according to m indication signals;
respectively receiving the m digital switching signals by m rows of second memory cells in the non-volatile perceptive memory array having m rows by q columns of second memory cells, wherein the m rows of second memory cells are respectively pre-configured with a number m of q-bit non-volatile perceptive symbols;
switching on a corresponding row of second memory cells to output a corresponding q-bit non-volatile perceptive symbol as a q-bit output symbol in response to one digital switching signal having a first voltage level; and
switching off a corresponding row of second memory cells in response to one digital switching signal having a second voltage level, wherein m, n and q are greater than one;
wherein each of the m rows by n columns of first memory cells and the m rows by q columns of second memory cells comprises a non-volatile memory (NVM) device pair, and each NVM device pair outputs one of a high operating voltage VDD and a ground voltage VSS of the digital perceptron device in response to two input voltages VDD and VSS.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the n-bit input symbol matches zero or one of the number m of pre-configured n-bit non-volatile content symbols so that zero or one of the number m of pre-configured q-bit non-volatile perceptive symbols is outputted as the q-bit output symbol.

### Claim 14 (depends on 12)

The method according to claim 12, wherein the step of respectively obtaining the m digital switching signals further comprises:
respectively obtaining the m digital switching signals based on the m indication signals in response to a first control signal, wherein the first control signal is activated when the digital perceptron device is turned on.

### Claim 15 (depends on 14)

The method according to claim 14, further comprising:
prior to the step of parallel comparing, temporarily storing an n-bit input signal; and
amplifying the n-bit input signal to obtain the n-bit input symbol according to the first control signal.

### Claim 16 (depends on 14)

The method according to claim 14, further comprising:
temporarily storing the q-bit output symbol according to the first control signal;
amplifying the q-bit output symbol to obtain a q-bit output signal; and
outputting the q-bit output signal in response to a second control signal, wherein the second control signal is activated when the n-bit input symbol matches one of the number m of pre-configured n-bit non-volatile content symbols.

### Claim 17 (depends on 12)

The method according to claim 12, wherein the q-bit output symbol is autonomously processed with the n-bit input symbol according to the number m of pre-configured n-bit non-volatile content symbols and the number m of pre-configured q-bit non-volatile perceptive symbols.

### Claim 18 (depends on 12)

The method according to claim 12, further comprising:
prior to the step of parallel comparing, configuring the non-volatile content memory array with the number m of n-bit non-volatile content symbols and the non-volatile perceptive memory array with the number m of q-bit non-volatile perceptive symbols according to at least one of coding efficiency and a learning algorithm.

### Claim 19 (depends on 12)

The method according to claim 12, further comprising:
after the steps of switching on and switching off, re-configuring the non-volatile content memory array with a number m of updated n-bit non-volatile content symbols and the non-volatile perceptive memory array with a number m of updated q-bit non-volatile perceptive symbols according to at least one of coding efficiency and a learning algorithm.