# US 2017/0256294 A1 · Semiconductor device

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- Number: US 2017/0256294 A1
- Document ID: US20170256294A1
- Status: Published application
- Kind: A1
- Application number: 15/599,041
- Filed: 2017-05-18
- Published: 2017-09-07
- Earliest claimed: 2016-01-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Chang Hyun KIM; Min Chang KIM; Do Yun LEE; Jae Jin LEE; Hun Sam JUNG
- Web page: https://patentgrep.com/patent/US20170256294A1

## CPC

- G11C 7/109: {Control signal input circuits}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 7/08: Control thereof
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/419: Read-write [R-W] circuits
- G11C 29/023: {in clock generator or timing circuitry}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive signals from the first chip to generate a latch address based on the received signals from the first chip.

## Claims

### Claim 1

A semiconductor device comprising:
an external signal-inputting circuit configured to receive and output an external clock, an external command and an external address;
a plurality of signal-transmitting circuits configured to output signals outputted from the external signal-inputting circuit as an internal clock, an internal command and an internal address based on a master enabling signal;
a command-delaying circuit configured to delay the internal command for a period of the internal clock;
another signal-transmitting circuit configured to output a signal outputted from the command-delaying circuit as a delay command based on the master enabling signal; and
an address-latching circuit configured to latch the internal address based on the internal command and to output a latched signal as a latch address based on the delay command.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the master enabling signal is enabled when a chip in the semiconductor device is operated as a master chip, and the master enabling signal is disabled when the chip is operated as a slave chip.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the plurality of signal-transmitting circuits output the signals outputted from the external signal-inputting circuit as the internal clock, the internal command and the internal address when the master enabling signal is enabled, and the plurality of signal-transmitting circuits block the signals outputted from the external signal-inputting circuit as the internal clock, the internal command and the internal address when the master enabling signal is disabled.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the another signal-transmitting circuit outputs the signal outputted from the command-delaying circuit as the delay command when the master enabling signal is enabled, and the another signal-transmitting circuit blocks the signal outputted from the command-delaying circuit as the delay command when the master enabling signal is disabled.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
an address decoder configured to decode the latch address; and
a command-processing circuit operated based on the delay command.