# US 2017/0256293 A1 · Sensing buffer, peripheral circuit, and/or memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256293 A1 - Document ID: US20170256293A1 - Status: Published application - Kind: A1 - Application number: 15/259,412 - Filed: 2016-09-08 - Published: 2017-09-07 - Earliest claimed: 2016-03-07 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Young Sub YUK - Web page: https://patentgrep.com/patent/US20170256293A1 ## CPC - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)} - H03K 5/249: {using clock signals} - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/08: Control thereof - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to a first current regardless of an external power supply and/or a temperature. ## Claims ### Claim 1 A sensing buffer, comprising: a first input circuit coupled between an external power supply and a ground voltage and configured to generate a first current according to a reference voltage; a first mirror circuit configured to maintain a predetermined current of a first node according to the first current regardless of the external power supply and a temperature applied to the sensing buffer; a second input circuit including a second node coupled to the first node, wherein a predetermined current of a third node is based on a sensing voltage and the current of the first and second nodes; and a resistor coupled between the first and second nodes and configured to maintain a predetermined current between the first and second input circuits. ### Claim 2 (depends on 1) The sensing buffer according to claim 1, wherein the first input circuit receives the external power supply through an external power supply terminal and generates a current path such that the first current flows between the external power supply terminal and a ground voltage terminal in response to the reference voltage. ### Claim 3 (depends on 1) The sensing buffer according to claim 1, wherein the second input circuit receives the external power supply and generates a current path between the external power supply and the ground voltage in response to the sensing voltage. ### Claim 4 (depends on 1) The sensing buffer according to claim 1, wherein the first mirror circuit operates in a saturation state such that a predetermined current of the first node flows. ### Claim 5 (depends on 1) The sensing buffer according to claim 1, further comprising: a second mirror circuit configured to maintain predetermined currents mirrored in the first mirror circuit. ### Claim 6 (depends on 5) The sensing buffer according to claim 5, further comprising: boosting circuits configured for amplifying an amount of an internal current based on a current flowing through the second mirror circuit. ### Claim 7 (canceled) ### Claim 8 A sensing buffer, comprising: a first input circuit coupled between an external power supply and a ground voltage and configured for generating a first current based on a reference voltage; a second input circuit coupled between the external power supply and the ground voltage and configured for generating a second current based on a sensing voltage; a first mirror circuit configured for operating in a saturation state between the first and second input circuits to maintain a predetermined current flowing through a first node and a second node; a second mirror circuit coupled to the ground voltage between the first and second input circuits and configured for generating a current path along with the first mirror circuit; a first boosting circuit coupled between the external power supply and the ground voltage and configured for boosting a current based on a potential of a third node coupled to the first node; and a second boosting circuit coupled between the external power supply and the ground voltage and configured for boosting the current based on a potential of a fourth node coupled to the second node. ### Claim 9 (depends on 8) The sensing buffer according to claim 8, wherein the first input circuit comprises: a first switch coupled between the external power supply and a fifth node and operating based on the reference voltage; a second switch coupled between the fifth node and the ground voltage and operating based on the potential of the third node; a third switch coupled between the external power supply and a sixth node and operating based on a potential of the sixth node; and a current generator coupled between the sixth node and the ground voltage and generating the current to the sixth node. ### Claim 10 (depends on 9) The sensing buffer according to claim 9, wherein the first and second switches are NMOS transistors and the third switch is a PMOS transistor. ### Claim 11 (depends on 9) The sensing buffer according to claim 9, further comprising: a first resistor coupled between the external power supply and the first switch. ### Claim 12 (depends on 9) The sensing buffer according to claim 9, wherein the second input circuit comprises: a fourth switch coupled between the external power supply and a seventh node and operating based on the sensing voltage; a fifth switch coupled between the seventh node and the ground voltage and operating based on the potential of the fourth node; a sixth switch coupled between the external power supply and an eighth node and operating based on a potential of the eighth node; and a second current generator coupled between the eighth node and the ground voltage and generating the current to the eighth node. ### Claim 13 (depends on 12) The sensing buffer according to claim 12, wherein the fourth and fifth switches are NMOS transistors and the sixth switch is a PMOS transistor. ### Claim 14 (depends on 12) The sensing buffer according to claim 12, further comprising: a second resistor coupled between the external power supply and the fourth switch. ### Claim 15 (depends on 12) The sensing buffer according to claim 12, further comprising: a third resistor coupled between the fifth node and the seventh node. ### Claim 16 (depends on 12) The sensing buffer according to claim 12, wherein the first mirror circuit comprises: a seventh switch coupled between the external power supply and the first node and operating based on a potential of a ninth node; an eighth switch coupled between the first node and the ninth node and operating based on the potential of the sixth node; a tenth switch coupled between the external power supply and the second node and operating based on a potential of a tenth node; an eleventh switch coupled between the first node and the third node and operating based on the potential of the eighth node; and a twelfth switch coupled between the second node and the fourth node and operating based on the potential of the sixth node. ### Claim 17 (depends on 16) The sensing buffer according to claim 16, wherein the seventh to twelfth switches are PMOS transistors. ### Claim 18 (depends on 16) The sensing buffer according to claim 16, wherein the second mirror circuit comprises: a thirteenth switch coupled between the fourth node and the ground voltage and operating based on a potential of an eleventh node; a fourteenth switch coupled between the third node and the ground voltage and operating based on the potential of the eleventh node; a first resistor coupled between the fourth node and the eleventh node; a second resistor coupled between the third node and the eleventh node; a third current generator coupled between the ninth node and the ground voltage and generating the current to the ninth node; and a fourth current generator coupled between the tenth node and the ground voltage and generating the current to the tenth node. ### Claim 19 (depends on 18) The sensing buffer according to claim 18, wherein the thirteenth and fourteenth switches are NMON transistor. ### Claim 20 A memory device, comprising: a memory cell array configured for storing data; a page buffer unit coupled to the memory cell array through bit lines and configured for sensing a current or a voltage of the bit lines; and a sensing buffer configured for generating a sensing voltage and applying the sensing voltage to the page buffer unit, wherein the sensing buffer includes switches included in a feedback current loop, and wherein the switches are operated in a saturation state based on a plurality of current paths.