# US 2017/0256291 A1 · Memory module with packages of stacked memory chips

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- Number: US 2017/0256291 A1
- Document ID: US20170256291A1
- Status: Published application
- Kind: A1
- Application number: 15/602,099
- Filed: 2017-05-22
- Published: 2017-09-07
- Earliest claimed: 2010-11-03
- Assignees: Netlist, Inc.
- Applicants: Netlist, Inc.
- Inventors: Hyun Lee
- Web page: https://patentgrep.com/patent/US20170256291A1

## CPC

- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory module is operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus. The memory module comprises a register device coupled to the command/address bus, and a plurality of DRAM packages coupled to the data bus and to the register device via a set of module control lines. Each respective DRAM package comprises stacked array dies and a control die. The control die includes data signal conduits and control signal conduits. In response to the memory module receiving a set of command/address signals from the system memory controller, the register device outputs control signals, and the control die configures the data signal conduits in accordance with the control signals to enable respective bits of one or more data signals to be communicated between a selected die among the stacked dies and the system memory controller.

## Claims

### Claim 1

A memory module operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus, comprising:
a register device to receive command/address signals from the system memory controller via the command/address bus and to output control signals in response to the input command/address signals, the control signals including chip-select signals; and
a plurality of DRAM packages coupled to the register device via a set of module control lines, each respective DRAM package comprising:
control terminals coupled to the module control lines via which the each respective DRAM package receives the control signals from the register device, and data terminals coupled to a respective section of the data bus via which the each respective DRAM package communicates with the system memory controller respective bits of one or more data signals associated with the command/address signals;
stacked array dies;
a control die including data signal conduits coupled to the data terminals and control signal conduits coupled to the control terminals, the control signal conduits including chip-select conduits for receiving the chip select signals and providing respective ones of the chip select signals to respective ones of the stacked array dies; and
die interconnects including first die interconnects coupled to the data signal conduits and second die interconnects coupled to the control signal conduits, at least one of the first die interconnects is coupled to at least two of the stacked array dies; and
wherein the control die configures the data signal conduits in accordance with the control signals to enable the respective bits of the one or more data signals to be communicated between a selected die among the stacked dies and the system memory controller, the selected die having received one of the chip select signals that is different from any of the other ones of the chip select signals.

### Claim 2 (depends on 1)

The memory module of claim 1, wherein the control die configures the data signal conduits to control data bus time slots for the respective bits of the one or more data signals.

### Claim 3 (depends on 1)

The memory module of claim 1, wherein the control die includes a data path control circuit that configures the data signal conduits in accordance with the control signals.

### Claim 4 (depends on 1)

The memory module of claim 1, wherein the control signals include command/address signals, wherein the control die includes command/address buffers to control the timing of the command/address signals in the control signals.

### Claim 5 (depends on 4)

The memory module of claim 4, wherein the command/address buffers comprise latches.

### Claim 6 (depends on 1)

The memory module of claim 1, wherein the data signal conduits include data buffers to control the timing of the respective bits of the one or more data signals.

### Claim 7 (depends on 6)

The memory module of claim 6, wherein control die configures the data signal conduits to control data bus time slots for the respective bits of the one or more data signals.

### Claim 8 (depends on 1)

The memory module of claim 1, wherein the array dies include DDR DRAM, SDRAM, flash memory, or SRAM.

### Claim 9 (depends on 1)

The memory module of claim 1, wherein the control dies is configured to decode the control signals to obtain command/address signals for providing to the array dies.

### Claim 10 (depends on 1)

The memory module of claim 1, wherein the control signals include decoded command/address signals, and wherein the control die is configured to pass the command/address signals through to the stacked array dies.