# US 2017/0256290 A1 · Stacked dram device and method of manufacture

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- Number: US 2017/0256290 A1
- Document ID: US20170256290A1
- Status: Published application
- Kind: A1
- Application number: 15/603,333
- Filed: 2017-05-23
- Published: 2017-09-07
- Earliest claimed: 2011-05-12
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Thomas Vogelsang
- Web page: https://patentgrep.com/patent/US20170256290A1

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 12/50: {Peripheral circuit region structures}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 90/00: Package configurations
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

## Claims

### Claim 1

A memory device comprising:
a first dynamic random access memory (DRAM) integrated circuit (IC) chip including
first memory core circuitry, and
first input/output (I/O) circuitry;
a second DRAM IC chip stacked vertically with the first DRAM IC chip, the second DRAM IC chip including
second memory core circuitry, and
second I/O circuitry; and
wherein solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein a first portion of the conductive path is formed in a metal layer, the metal layer formed solely on one of the first DRAM IC chip or the second DRAM IC chip.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the metal layer comprises:
a redistribution layer formed during a packaging process.

### Claim 4 (depends on 2)

The memory device according to claim 2, wherein a second portion of the conductive path is formed in at least one through-silicon-via (TSV).

### Claim 5 (depends on 4)

The memory device according to claim 4, wherein:
the first memory core circuitry and the second memory core circuitry are coupled to solely one of the first I/O circuitry or the second I/O circuitry via the metal layer and the at least one TSV.

### Claim 6 (depends on 1)

The memory device according to claim 1 wherein:
solely one of the first I/O circuitry or the second I/O circuitry is configured to communicate with a memory controller.

### Claim 7 (depends on 1)

The memory device according to claim 1 further comprising:
a third DRAM IC chip stacked with the first DRAM IC chip and the second DRAM IC chip, the third DRAM IC chip including
third memory core circuitry,
third I/O circuitry electrically isolated from the third memory core circuitry; and
wherein the conductive path electrically couples to the third memory core circuitry.

### Claim 8

A memory module comprising:
a substrate; and
multiple memory devices mounted to the substrate, each memory device comprising
a first dynamic random access memory (DRAM) integrated circuit (IC) chip including
first memory core circuitry, and
first input/output (I/O) circuitry;
a second DRAM IC chip stacked vertically with the first DRAM IC chip, the second DRAM IC chip including
second memory core circuitry, and
second I/O circuitry; and
wherein solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

### Claim 9 (depends on 8)

The memory module according to claim 8, wherein a first portion of the conductive path is formed in a metal layer, the metal layer formed solely on one of the first DRAM IC chip or the second DRAM IC chip.

### Claim 10 (depends on 9)

The memory module according to claim 9, wherein the metal layer comprises:
a redistribution layer formed during a packaging process.

### Claim 11 (depends on 9)

The memory module according to claim 9, wherein a second portion of the conductive path is formed in at least one through-silicon-via (TSV).

### Claim 12 (depends on 11)

The memory module according to claim 11, wherein:
the first memory core circuitry and the second memory core circuitry are coupled to solely one of the first I/O circuitry or the second I/O circuitry via the metal layer and the at least one TSV.

### Claim 13 (depends on 1)

The memory module according to claim 1, wherein:
solely one of the first I/O circuitry or the second I/O circuitry is configured to communicate with a memory controller.

### Claim 14 (depends on 1)

The memory module according to claim 1, each memory device further comprising:
a third DRAM IC chip stacked with the first DRAM IC chip and the second DRAM IC chip, the third DRAM IC chip including
third memory core circuitry,
third I/O circuitry electrically isolated from the third memory core circuitry; and
wherein the conductive path electrically couples to the third memory core circuitry.

### Claim 15

A memory device comprising:
a first dynamic random access memory (DRAM) integrated circuit (IC) chip including
first memory core circuitry, and
first input/output (I/O) circuitry;
a second DRAM IC chip stacked vertically with the first DRAM IC chip, the second DRAM IC chip including
second memory core circuitry, and
second I/O circuitry; and
wherein solely one of the first DRAM IC chip or the second DRAM IC chip includes means for electrically coupling at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

### Claim 16 (depends on 15)

The memory device according to claim 15, wherein the means for electrically coupling comprises:
a conductive path formed in a metal layer, the metal layer formed solely on one of the first DRAM IC chip or the second DRAM IC chip; and
at least one through-silicon via (TSV) electrically connected to the metal layer.

### Claim 17 (depends on 16)

The memory device according to claim 16, wherein the metal layer comprises a redistribution layer formed during a packaging process.

### Claim 18 (depends on 16)

The memory device according to claim 16, further comprising power distribution conductors formed in the metal layer.

### Claim 19 (depends on 16)

The memory device according to claim 16, further comprising a test pad formed in the metal layer.

### Claim 20 (depends on 16)

The memory device according to claim 16 wherein solely one of the first I/O circuitry or the second I/O circuitry is configured to communicate with a memory controller.