# US 2017/0256223 A1 · Gate driver and liquid crytal display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256223 A1 - Document ID: US20170256223A1 - Status: Published application - Kind: A1 - Application number: 14/908,403 - Filed: 2016-01-11 - Published: 2017-09-07 - Earliest claimed: 2015-12-28 - Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Inventors: Peng DU - Web page: https://patentgrep.com/patent/US20170256223A1 ## CPC - G09G 3/3677: {suitable for active matrices only} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0205: Simultaneous scanning of several lines in flat panels - G09G 2310/0213: controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The present invention proposes a gate driver including a plurality of gate driver on array (GOA) units. Each of the GOA unit includes a main driving circuit, a starting signal output circuit, and a plurality of gate driving circuits. The gate driver utilizes a starting signal and two inversed clock signals to control the charging period and the discharging period of the gate driver. Furthermore, the gate driver utilizes multiple clock signals to control the output of the gate driving signals. In this way, the number of the clock signals is reduced and thus the power consumption is also reduced. ## Claims ### Claim 1 A gate driver comprising a plurality of gate driver on array (GOA) units, each of the GOA unit comprising: a main driving circuit, comprising: a first transistor, comprising a source, a drain, and a gate, wherein the source of the first transistor is configured to receive a starting signal and the gate of the first transistor is configured to receive a first triggering clock signal; a second transistor, comprising a source, a drain, and a gate, wherein the gate of the second transistor is configured to receive a second triggering clock signal; and a third transistor, comprising a source, a drain, and a gate, wherein the main driving circuit has a first control node and a second control node and is configured to generate a charging signal on the first control node and generate a control signal on the second control node in response to the starting signal, the first triggering clock signal and the second clock signal; a starting signal output circuit, comprising: a fourth transistor, configured to receive the charging signal to output an intermediate signal; and a fifth transistor, configured to receive the control signal to deactivate the intermediate signal; and a plurality of gate driving circuits, each of the gate driving circuit comprising: a sixth transistor, configured to receive the charging signal to output a gate driving signal; and a seventh transistor, configured to receive the control signal to deactivate the gate driving signal. ### Claim 2 (depends on 1) The gate driver of claim 1, wherein the starting signal is another intermediate signal transferred from a GOA unit of a previous stage or a starting signal provided by a gate driving control chip. ### Claim 3 (depends on 1) The gate driver of claim 1, wherein the first triggering clock signal and the second triggering clock signal are inversed. ### Claim 4 (depends on 1) The gate driver of claim 1, wherein the main driving circuit further comprises an eighth transistor, a ninth transistor, and a tenth transistor, and wherein when the first transistor is turned on by the first triggering clock signal, the eighth transistor, the ninth transistor, and the tenth transistor are turned on such that the charging signal is generated on the first control node and the control signal is generated on the second control node. ### Claim 5 (depends on 1) The gate driver of claim 1, wherein each of the sixth transistors of the gate driving circuits comprises a source, a drain, and a gate, wherein the sources of the sixth transistors are respectively electrically connected to different clock signals, the gates are electrically connected to the charging signal, and wherein the drains of the sixth transistors sequentially output a gate driving signal when the sixth transistors are turned on in response to the clock signals. ### Claim 6 (depends on 5) The gate driver of claim 5, wherein each of the seventh transistors of the gate driving circuits comprises a source, a drain, and a gate, wherein the sources of the seventh transistors are respectively electrically connected to the drains of the sixth transistors, the drains of the seventh transistors are electrically connected to a voltage source, the gates of the seventh transistors receive the control signal, and wherein the seventh transistors deactivate the gate driving signals by conducting the first voltage source when the seventh transistors are turned on in response to the control signal. ### Claim 7 (depends on 1) The gate driver of claim 1, wherein the fourth transistor of the starting signal output circuit comprises a source, a drain, and a gate, wherein the source of the fourth transistor is electrically connected to the second triggering clock signal, the gate of the fourth transistor receives the charging signal, and wherein when the fourth transistor is turned on by the second triggering clock signal, the drain of the fourth transistor outputs the starting signal. ### Claim 8 (depends on 7) The gate driver of claim 7, wherein the fifth transistor of the starting signal output circuit comprises a source, a drain, and a gate, the source of the fifth transistor is electrically connected to the drain of the fourth transistor, the drain of the fifth transistor is electrically connected to the first voltage source, and the gate of the fifth transistor receives the control signal, and wherein when the fifth transistor is turned on by control signal, the fifth transistor deactivate the starting signal by conducting the first voltage source. ### Claim 9 (depends on 1) The gate driver of claim 1, wherein each of the GOA unit comprises a sequential-scan transistor and a reversed-scan transistor, respectively configured to receive a sequential-scan control signal and a reversed-scan control signal to control the GOA unit to operate in a sequential-scan mode or a reversed-scan mode. ### Claim 10 A liquid crystal display comprising a gate driver, the gate driver comprising a plurality of gate driver on array (GOA) units, each of the GOA unit comprising: a main driving circuit, comprising: a first transistor, comprising a source, a drain, and a gate, wherein the source of the first transistor is configured to receive a starting signal and the gate of the first transistor is configured to receive a first triggering clock signal; a second transistor, comprising a source, a drain, and a gate, wherein the gate of the second transistor is configured to receive a second triggering clock signal; and a third transistor, comprising a source, a drain, and a gate, wherein the main driving circuit has a first control node and a second control node and is configured to generate a charging signal on the first control node and generate a control signal on the second control node in response to the starting signal, the first triggering clock signal and the second clock signal; a starting signal output circuit, comprising: a fourth transistor, configured to receive the charging signal to output an intermediate signal; and a fifth transistor, configured to receive the control signal to deactivate the intermediate signal; and a plurality of gate driving circuits, each of the gate driving circuit comprising: a sixth transistor, configured to receive the charging signal to output a gate driving signal; and a seventh transistor, configured to receive the control signal to deactivate the gate driving signal. ### Claim 11 (depends on 10) The liquid crystal display of claim 10, wherein the starting signal is another intermediate signal transferred from a GOA unit of a previous stage or a starting signal provided by a gate driving control chip. ### Claim 12 (depends on 10) The liquid crystal display of claim 10, wherein the first triggering clock signal and the second triggering clock signal are inversed. ### Claim 13 (depends on 10) The liquid crystal display of claim 10, wherein the main driving circuit further comprises an eighth transistor, a ninth transistor, and a tenth transistor, and wherein when the first transistor is turned on by the first triggering clock signal, the eighth transistor, the ninth transistor, and the tenth transistor are turned on such that the charging signal is generated on the first control node and the control signal is generated on the second control node. ### Claim 14 (depends on 10) The liquid crystal display of claim 10, wherein each of the sixth transistors of the gate driving circuits comprises a source, a drain, and a gate, wherein the sources of the sixth transistors are respectively electrically connected to different clock signals, the gates are electrically connected to the charging signal, and wherein the drains of the sixth transistors sequentially output a gate driving signal when the sixth transistors are turned on in response to the clock signals. ### Claim 15 (depends on 14) The liquid crystal display of claim 14, wherein each of the seventh transistors of the gate driving circuits comprises a source, a drain, and a gate, wherein the sources of the seventh transistors are respectively electrically connected to the drains of the sixth transistors, the drains of the seventh transistors are electrically connected to a voltage source, the gates of the seventh transistors receive the control signal, and wherein the seventh transistors deactivate the gate driving signals by conducting the first voltage source when the seventh transistors are turned on in response to the control signal. ### Claim 16 (depends on 10) The liquid crystal display of claim 10, wherein the fourth transistor of the starting signal output circuit comprises a source, a drain, and a gate, wherein the source of the fourth transistor is electrically connected to the second triggering clock signal, the gate of the fourth transistor receives the charging signal, and wherein when the fourth transistor is turned on by the second triggering clock signal, the drain of the fourth transistor outputs the starting signal. ### Claim 17 (depends on 16) The liquid crystal display of claim 16, wherein the fifth transistor of the starting signal output circuit comprises a source, a drain, and a gate, the source of the fifth transistor is electrically connected to the drain of the fourth transistor, the drain of the fifth transistor is electrically connected to the first voltage source, and the gate of the fifth transistor receives the control signal, and wherein when the fifth transistor is turned on by control signal, the fifth transistor deactivate the starting signal by conducting the first voltage source. ### Claim 18 (depends on 10) The liquid crystal display of claim 10, wherein each of the GOA unit comprises a sequential-scan transistor and a reversed-scan transistor, respectively configured to receive a sequential-scan control signal and a reversed-scan control signal to control the GOA unit to operate in a sequential-scan mode or a reversed-scan mode.