# US 2017/0256221 A1 · Gate driver on array substrate and liquid crystal display adopting the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256221 A1 - Document ID: US20170256221A1 - Status: Published application - Kind: A1 - Application number: 14/905,024 - Filed: 2015-12-23 - Published: 2017-09-07 - Earliest claimed: 2015-10-15 - Assignees: Wuhan China Star Opyoelectronics Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Technology Co. Ltd. - Inventors: Yafeng Li - Web page: https://patentgrep.com/patent/US20170256221A1 ## CPC - G09G 3/3677: {suitable for active matrices only} - G11C 19/184: {with field-effect transistors, e.g. MOS-FET} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A GOA substrate includes N shift register units. The first stage shift register unit outputs a scan signal pulse based on a first clock signal and a start signal. The last stage shift register unit outputs a scan signal pulse based on Mth clock signal and the start signal. The start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame. Since the first and last shift register units are used to drive a scan signal pulse based on the start signal, the present invention reduces the number of wires needed to transmit start signals and simplifies the complexity of the layout design. ## Claims ### Claim 1 A gate driver on array (GOA) substrate, comprising: a plurality of pixel units arranged in an array; a plurality of transistors, each electrically connected to one of the pixel units; and N shift register units, connected in cascade, with each M shift register units controlled by M clock signals; a first stage shift register unit outputs a scan signal pulse from an output terminal based on a first clock signal and a start signal; a last stage shift register unit outputs a scan signal pulse from the output terminal based on a Mth clock signal and the start signal, where N and M are positive integers, and N is larger than M; wherein the start signal has a frequency equal to a frame rate to display a frame; the M clock signals output signal pulses alternately, and the outputting time is not overlapped; the start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame; the second frame is the frame following the first frame. ### Claim 2 (depends on 1) The GOA substrate of claim 1, wherein each shift register unit comprises: a pull-up circuit, comprising a first transistor, with a gate coupled to a first node, a source coupled to the clock signals, a drain coupled to the output terminal, so to output the scan signal pulse from the output terminal based on the clock signals; a pull-up control circuit, comprising a second transistor, with a gate coupled to an output terminal of a previous stage shift register unit of each shift register unit, a source coupled to a first supply voltage, and a drain coupled to the first node, so to turn on the pull-up circuit based on the scan signal pulse of the previous shift register unit of each shift register unit; a boost circuit, coupled between the first node and the output terminal, for boosting the electric potential of the first node; a pull-down holding circuit, coupled to the first node, the clock signal and a second supply voltage, for holding the first node at a low level; and a pull-down circuit, coupled to the second supply voltage, the output terminal and the output terminal of the next shift register unit of each shift register unit, for pulling down the electric potential of the first node to the second supply voltage. ### Claim 3 (depends on 2) The GOA substrate of claim 2, wherein the pull-down circuit comprises: a third transistor, comprising a drain electrically connected to the output terminal, a source electrically connected to the second supply voltage; and a fourth transistor, comprising a drain electrically connected to the first node, a source electrically connected to the second supply voltage, and a gate electrically connected to the gate of the third transistor. ### Claim 4 A gate driver on array (GOA) substrate, comprising: a plurality of pixel units arranged in an array; a plurality of transistors, each electrically connected to one of the pixel units; and N shift register units, connected in cascade, with each M shift register units controlled by M clock signals; the first stage shift register unit outputs a scan signal pulse from the output terminal based on a first clock signal and a start signal; the last stage shift register unit outputs a scan signal pulse from an output terminal based on a Mth clock signal and the start signal, where N and M are positive integers, and N is larger than M; wherein the start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame; the second frame is the frame following the first frame. ### Claim 5 (depends on 4) The GOA substrate of claim 4, wherein the start signal has a frequency equal to a frame rate. ### Claim 6 (depends on 4) The GOA substrate of claim 4, wherein the M clock signals output signal pulses alternately, and the outputting time is not overlapped. ### Claim 7 (depends on 4) The GOA substrate of claim 4, wherein each shift register unit comprises: a pull-up circuit, comprising a first transistor, with a gate coupled to a first node, a source coupled to the clock signals, a drain coupled to the output terminal, so to output scan signal pulse from the output terminal based on the clock signals; a pull-up control circuit, comprising a second transistor, with a gate coupled to the output terminal of a previous shift register unit of each shift register unit, a source coupled to a first supply voltage, and a drain coupled to the first node, so to turn on the pull-up circuit based on the scan signal pulse of the previous shift register unit of each shift register unit; a pull-down holding circuit, coupled to the first node, the clock signal and a second supply voltage, for holding the first node at a low level; and a pull-down circuit, coupled to the second supply voltage, the output terminal and the output terminal of the next shift register unit of each shift register unit, for pulling down the electric potential of the first node to the second supply voltage. ### Claim 8 (depends on 7) The GOA substrate of claim 7, wherein the shift register unit further comprises a boost circuit, coupled to the first node and the output terminal, to boost the electric potential of the first node. ### Claim 9 (depends on 8) The GOA substrate of claim 8, wherein the pull-down circuit comprises: a third transistor, comprising a drain electrically connected to the output terminal, a source electrically connected to the second supply voltage; and a fourth transistor, comprising a drain electrically connected to the first node, a source electrically connected to the second supply voltage, and a gate electrically connected to the gate of the third transistor. ### Claim 10 A liquid crystal display, comprising: a source driver, for outputting data signal to a plurality of pixel units to show images; and a gate driver on array (GOA) substrate, for outputting scan signals to turn on a plurality of transistors, the GOA substrate comprising: N shift register units, connected in cascade, with each M shift register units controlled by M clock signals; the first stage shift register unit outputs a scan signal pulse from the output terminal based on a first clock signal and a start signal; the last stage shift register unit outputs a scan signal pulse from an output terminal based on a Mth clock signal and the start signal, where N and M are positive integers, and N is larger than M; wherein the start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame; the second frame is the frame following the first frame. ### Claim 11 (depends on 10) The liquid crystal display of claim 10, wherein the start signal has a frequency equal to a frame rate. ### Claim 12 (depends on 10) The liquid crystal display of claim 10, wherein the M clock signals output signal pulses alternately, and the outputting time is not overlapped. ### Claim 13 (depends on 10) The liquid crystal display of claim 10, wherein each shift register unit comprises: a pull-up circuit, comprising a first transistor, with a gate coupled to a first node, a source coupled to the clock signals, a drain coupled to the output terminal, so to output scan signal pulse from the output terminal based on the clock signals; a pull-up control circuit, comprising a second transistor, with a gate coupled to the output terminal of a previous shift register unit of each shift register unit, a source coupled to a first supply voltage, and a drain coupled to the first node, so to turn on the pull-up circuit based on the scan signal pulse of the previous shift register unit of each shift register unit; a pull-down holding circuit, coupled to the first node, the clock signal and a second supply voltage, for holding the first node at a low level; and a pull-down circuit, coupled to the second supply voltage, the output terminal and the output terminal of the next shift register unit of each shift register unit, for pulling down the electric potential of the first node to the second supply voltage. ### Claim 14 (depends on 13) The liquid crystal display of claim 13, wherein the shift register unit further comprises a boost circuit, coupled to the first node and the output terminal, to boost the electric potential of the first node. ### Claim 15 (depends on 14) The liquid crystal display of claim 14, wherein the pull-down circuit comprises: a third transistor, comprising a drain electrically connected to the output terminal, a source electrically connected to the second supply voltage; and a fourth transistor, comprising a drain electrically connected to the first node, a source electrically connected to the second supply voltage, and a gate electrically connected to the gate of the third transistor.