# US 2017/0256019 A1 · Method and Apparatus for Efficient Submission of Workload to a High Performance Graphics Sub-System

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0256019 A1
- Document ID: US20170256019A1
- Status: Published application
- Kind: A1
- Application number: 15/062,691
- Filed: 2016-03-07
- Published: 2017-09-07
- Earliest claimed: 2016-03-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Balaji Vembu; Kritika Bala; Murali Ramadoss; Hema Nalluri; Jeffery Boles; Jeffrey Frizzell; Joseph Koston
- Web page: https://patentgrep.com/patent/US20170256019A1

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 2009/45579: {I/O management, e.g. providing access to device drivers or storage}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.

## Claims

### Claim 1

An apparatus comprising:
a graphics processing subsystem including one or more graphics engines; and
a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem, the graphics scheduler to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.

### Claim 2 (depends on 1)

The apparatus as in claim 1, wherein the submission queue has a maximum number of elements to reference the multiple work items and the graphics scheduler is to submit the submission queue to the graphics engine with less than the maximum number of elements.

### Claim 3 (depends on 2)

The apparatus as in claim 2, wherein the graphics scheduler is to append additional work items after the submission queue is submitted.

### Claim 4 (depends on 1)

The apparatus as in claim 1, wherein the one or more graphics engines are to execute the multiple work items in the submission queue in an execution queue after the graphics scheduler explicitly submits the submission queue.

### Claim 5 (depends on 4)

The apparatus as in claim 4, wherein the graphics schedule is to write to the memory mapped address and cause one of the one or more graphics engines of the graphics processing subsystems to pre-empt an executing work item.

### Claim 6 (depends on 5)

The apparatus as in claim 5, wherein the one or more graphics engines are to pre-empt the existing work item and transition to an idle state.

### Claim 7 (depends on 6)

The apparatus as in claim 6, wherein the graphics processing subsystem includes context storage memory to store information associated with an executing context of a graphics engine that is pre-empted and transitioned to the idle state is to store context information associated with the executing work item to context storage memory before the transition to the idle state.

### Claim 8 (depends on 7)

The apparatus as in claim 7, wherein the one of the one or more graphics engines that is pre-empted and transitioned to the idle state is to store the execution queue to the submission queue as a partially executed submission queue before the transition to the idle state, and the graphics processing system is further to transition the graphics engine to a low power state after the transition to the idle state.

### Claim 9 (depends on 8)

The apparatus as in claim 8, wherein the graphics processing subsystem is to transition the idle graphics engine to an operational state and the graphics scheduler is to re-submit the partially executed submission queue to the graphics engine via a register write.

### Claim 10

A non-transitory machine readable medium storing instructions which, when executed by one or more processors, causes the one or more processors to perform operations to schedule work items for one or more graphics engines within a graphics processing subsystem, the operations including:
receiving an identifier for a batch of one or more work items for submission to a graphics engine;
selecting which of the one or more graphics engines to which the batch of one or more work items is to be submitted;
inserting the identifier for the batch of one or more work items into an element of a submission queue associated with a selected graphics engine; and
explicitly submitting the elements in the submission queue by writing to a control register.

### Claim 11 (depends on 10)

The non-transitory machine readable medium as in claim 10, wherein the elements in the submission queue are submitted upon completion of an execution queue of the selected graphics engine.

### Claim 12 (depends on 11)

The non-transitory machine readable medium as in claim 11, the operations additionally including:
writing to a pre-empt selector of the control register when submitting the elements in the submission queue to halt execution of elements in the execution queue of the selected graphics engine; and
beginning execution of the elements in the submission queue.

### Claim 13 (depends on 12)

The non-transitory machine readable medium as in claim 12, the operations additionally including copying the elements from the submission queue to the execution queue before beginning the execution of the elements.

### Claim 14 (depends on 10)

The non-transitory machine readable medium as in claim 10, the operations additionally including:
writing to a pre-empt to idle selector of the control register to cause the graphics engine to halt execution of the elements in an execution queue and copy the elements of the execution queue to the submission queue as a partially executed submission queue before transitioning to an idle state; and
transitioning an idle graphics engine to a low power state.

### Claim 15 (depends on 14)

The non-transitory machine readable medium as in claim 14, the operations additionally including transitioning a graphics engine in a low power state to an operational state and resuming execution of the execution queue by re-submitting the partially executed submission queue.

### Claim 16

A graphics processing system comprising:
a first processor including one or more graphics engines;
a second processor coupled to the first processor on a single die; and
a microcontroller including scheduling logic to schedule operations for the one or more graphics engines, the scheduling logic configured to schedule a submission queue of multiple work items for execution on the one or more graphics engines, the scheduling logic to build the submission queue via a write to a memory mapped address that is mapped to the first processor and explicitly submit the submission queue to the graphics engine after the build of the submission queue.

### Claim 17 (depends on 16)

The graphics processing system as in claim 16, wherein the submission queue has a maximum number of elements to reference the multiple work items and the scheduling logic is to submit the submission queue to the graphics engine with less than the maximum number of elements.

### Claim 18 (depends on 17)

The graphics processing system as in claim 17, wherein the scheduling logic is to append additional work items after the submission queue is submitted.

### Claim 19 (depends on 16)

The graphics processing system as in claim 16, wherein the one or more graphics engines are to execute the multiple work items in the submission queue in an execution queue after the scheduling logic explicitly submits the submission queue.

### Claim 20 (depends on 19)

The graphics processing system as in claim 19, wherein the scheduling logic is to write to the memory mapped address and cause a graphics engine of the one or more graphics engines to pre-empt an executing work item and transition to an idle state.