# US 2017/0255507 A1 · Technologies for Estimating Remaining Life of Integrated Circuits Using On-Chip Memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0255507 A1 - Document ID: US20170255507A1 - Status: Published application - Kind: A1 - Application number: 15/446,776 - Filed: 2017-03-01 - Published: 2017-09-07 - Earliest claimed: 2016-03-01 - Assignees: Georgia Tech Research Corporation - Applicants: Georgia Tech Research Corporation - Inventors: Linda Milor; Woongrae Kim; Taizhi Liu - Web page: https://patentgrep.com/patent/US20170255507A1 ## CPC - G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)} - G06F 11/008: {Reliability or availability analysis} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 29/12005: {comprising voltage or current generators} - G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells - G11C 29/50004: {of threshold voltage} - G11C 29/50016: {of retention} - G11C 29/70: {Masking faults in memories by using spares or by reconfiguring} - G11C 2029/1208: {Error catch memory} - G11C 2029/3602: {Pattern generator} - G11C 2029/5002: {Characteristic} - G11C 2029/5004: {Voltage} - G11C 2029/5006: {Current} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and systems have been proposed to estimate the remaining lifetime of an electronic integrated circuit that incorporates error-correcting code memory by using the failed memory bits as an indicator for the remaining lifetime of the circuit. The number of failed memory bits correlates with the remaining lifetime of the circuit, but varies as a function of wearout mechanism and use conditions. The methodology incorporates algorithms and test patterns to diagnose the cause of memory cell failure. By linking the failed bits to the wearout mechanism and by using lifetime simulation, the remaining lifetime of the circuit is estimated. ## Claims ### Claim 1 A processor-implemented method for estimating a remaining lifetime of an electronic integrated circuit where the electronic integrated circuit includes memory, the method comprising: performing a diagnostic on a fault in the memory, generating, based on the performed diagnostic, a statistical model of time to failure of the memory, generating, based on the statistical model of time to failure of the memory, a statistical model of time to failure of the electronic integrated circuit; and estimating, based on the statistical model of time to failure of the electronic integrated circuit, the remaining lifetime of the electronic integrated circuit. ### Claim 2 (depends on 1) The method of claim 1, wherein the electronic integrated circuit is one of a microprocessor, microcontroller, or a system on a chip (SoC). ### Claim 3 (depends on 1) The method of claim 1, wherein the statistical model of time to failure of the memory is either a Weibull distribution or a Lognormal distribution, and the statistical model of time to failure of the electronic integrated circuit is either a Weibull distribution or a Lognormal distribution. ### Claim 4 (depends on 1) The method of claim 1, wherein the estimating is further based on use scenarios. ### Claim 5 (depends on 1) The method of claim 1, further including a detecting of the fault in the memory, where the detecting comprises using one or more of the following: a paired comparison between cells in an upper bank and a lower bank in a same sector of the memory to analyze bitline current of the memory, error-correcting code data, or a built-in self test (BIST) system. ### Claim 6 A processor-implemented method for estimating a remaining lifetime of an electronic integrated circuit where the electronic integrated circuit includes one or more circuit blocks comprising redundant circuitry, the method comprising: detecting a fault in one of the one or more circuit blocks comprising redundant circuitry, classifying the fault into one or more wearout mechanisms, generating, based on the classification of the fault, a statistical model of time to failure of the one or more circuit blocks comprising redundant circuitry containing the fault, generating, based on the statistical model of time to failure of the one or more circuit blocks comprising redundant circuitry containing the fault, a statistical model of time to failure of the electronic integrated circuit; and estimating, based on the statistical model of time to failure of the electronic integrated circuit, the remaining lifetime of the electronic integrated circuit. ### Claim 7 (depends on 6) The method of claim 6, wherein the estimating is further based on use scenarios. ### Claim 8 (depends on 6) The method of claim 6, wherein the one or more wearout mechanisms comprise one or more from the set of backend dielectric breakdown (BTDDB), gate oxide breakdown (GOBD), electromigration (EM), stress-induced voiding (SIV), hot carrier injection (HCI), time-dependent gate oxide breakdown (GTDDB), middle-of-line time-dependent dielectric breakdown (MTDDB), negative bias temperature instability (NBTI), or positive bias temperature instability (PBTI). ### Claim 9 (depends on 6) The method of claim 6, wherein the classifying of the fault into the one or more wearout mechanisms comprises determining a location of the fault. ### Claim 10 (depends on 6) The method of claim 6, wherein the classifying of the fault into the one or more wearout mechanisms comprises providing one or more electrical signals to the circuit block comprising redundant circuitry containing faults and monitoring one or more electrical test points within the circuit block comprising redundant circuitry containing the fault. ### Claim 11 (depends on 6) The method of claim 6, wherein the classifying of the fault into the one or more wearout mechanisms is based at least in part on expected failure rates due to one or more of the wearout mechanisms in the circuit block comprising redundant circuitry containing the fault. ### Claim 12 (depends on 6) The method of claim 6, wherein the detecting of the fault comprises using one or more of the following: error-correcting code data, or providing one or more electrical signals to the circuit block comprising redundant circuitry containing faults and monitoring one or more electrical test points within the circuit block comprising redundant circuitry containing the fault. ### Claim 13 An electronic system in communication with a memory, wherein an electronic integrated circuit is comprised at least in part of the memory, the electronic system comprising: a controller; a test pattern generator; and an output response analyzer, wherein the electronic system is configured to estimate a remaining lifetime of the electronic integrated circuit by: performing a diagnostic on a fault in the memory, generating, based on the performed diagnostic, a statistical model of time to failure of the memory, generating, based on the statistical model of time to failure of the memory, a statistical model of time to failure of the electronic integrated circuit; and estimating, based on the statistical model of time to failure of the electronic integrated circuit, the remaining lifetime of the electronic integrated circuit. ### Claim 14 (depends on 13) The electronic system of claim 13, wherein a detecting of the fault in the memory comprises using on or more of the following: a paired comparison between cells in an upper bank and a lower bank in a same sector of the memory to analyze bitline current of the memory, error-correcting code data. ### Claim 15 (depends on 13) The electronic system of claim 13, wherein the electronic integrated circuit comprises a first memory module and a second memory module, the first memory module having a first cache size and a first operating frequency, the second memory module having a second cache size and a second operating frequency, the second cache size differs from the first cache size, the second operating frequency differs from the first operating frequency, or both the second cache size differs from the first cache size and the second operating frequency differs from the first operating frequency, and the electronic system is further configured to perform the diagnostic on both the first module and the second module. ### Claim 16 (depends on 13) The electronic system of claim 13, wherein the diagnostic is configured to gather data related to one or more wearout mechanisms. ### Claim 17 (depends on 16) The electronic system of claim 16, wherein the performing the diagnostic on the memory comprises communicating a sequence of read and write commands to the memory. ### Claim 18 A method for updating a physical model of a wearout mechanism, the method comprising: detecting a fault in a circuit block containing redundant circuitry, providing one or more electrical signals to the circuit block containing redundant circuitry containing the fault, monitoring one or more electrical test points within the circuit block containing redundant circuitry containing the fault, wherein the one or more electrical test points provide an output in response to the providing of the one or more electrical signals, classifying, based on the monitoring of the one or more electrical test points proving the output, the fault into one of a plurality of wearout mechanisms, recording the wearout mechanism in which the fault was classified and a time to failure of the fault, and transmitting the recorded wearout mechanism and the time to failure of the fault wherein the transmitted wearout mechanism and the time to failure of the fault is used to update the physical model of the wearout mechanism in which the fault is classified. ### Claim 19 (depends on 18) The method of claim 18, wherein the transmitting of the recorded wearout mechanism and time to failure of the fault is used to update values of one or more fitting parameters, one or more constants, or at least one fitting parameter and at least one constant of the physical model of the wearout mechanism in which the fault is classified. ### Claim 20 (depends on 18) The method of claim 18, wherein a first electronic integrated circuit includes the circuit block containing redundant circuitry, further generating, based on the updated statistical model of the wearout mechanism, a statistical model of time to failure of a second circuit block included in a second electronic integrated circuit.