# US 2017/0255463 A1 · Operation of a multi-slice processor implementing dynamic switching of instruction issuance order > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0255463 A1 - Document ID: US20170255463A1 - Status: Published application - Kind: A1 - Application number: 15/059,853 - Filed: 2016-03-03 - Published: 2017-09-07 - Earliest claimed: 2016-03-03 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: JEFFREY C. BROWNSCHEIDLE; SUNDEEP CHADHA; MAUREEN A. DELANEY; DHIVYA JEGANATHAN; DUNG Q. NGUYEN; SALIM A. SHAH - Web page: https://patentgrep.com/patent/US20170255463A1 ## CPC - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters} - G06F 11/3006: {where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50)} - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags} - G06F 9/3865: {using deferred exception handling, e.g. exception flags} - G06F 9/3867: {using instruction pipelines} - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Operation of a multi-slice processor that includes execution slices implementing dynamic switching of instruction issuance order. Such a multi-slice processor includes determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor; responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions; and responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions. ## Claims ### Claim 1 A method of operation of a multi-slice processor, the multi-slice processor including a plurality of execution slices, the method comprising: determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor; responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions; and responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions. ### Claim 2 (depends on 1) The method of claim 1, wherein the operating condition comprises one of: a normal operating condition, a system hang condition, and a system recovery condition. ### Claim 3 (depends on 2) The method of claim 2, wherein determining the alternate issuance order is dependent upon both the change in the operating condition and the current issuance order. ### Claim 4 (depends on 3) The method of claim 3, wherein determining the alternate issuance order comprises: if the current issuance is out-of-order issuance and the operating condition is a system hang condition: determining the alternate issuance order to be in-order issuance; if the current issuance is out-of-order issuance and the operating condition is a system recovery condition: determining the alternate issuance order to be in-order issuance; if the current issuance is in-order issuance and a previous operating condition is a system hang condition: determining the alternate issuance order to be out-of-order issuance; and if the current issuance is in-order issuance and a previous operating condition is a system recovery condition: determining the alternate issuance order to be out-of-order issuance. ### Claim 5 (depends on 1) The method of claim 1, wherein the multi-slice processor comprises an issue queue and an instruction sequencing unit, and wherein the instruction sequencing unit includes an age array indicating relative ages of each instruction in an issue queue relative to each other instruction in the issue queue. ### Claim 6 (depends on 5) The method of claim 5, wherein each row of the age array corresponds to an entry in the issue queue, and wherein a first value at a particular row and a particular column indicates that the instruction in the issue queue corresponding to the particular row is younger than the instruction in the issue queue at the particular column. ### Claim 7 (depends on 6) The method of claim 6, further comprising: responsive to the alternate issuance order being an in-order issuance order, determining, in dependence upon the age array, an in-order sequence for the plurality of instructions. ### Claim 8 A multi-slice processor comprising: a plurality of execution slices, wherein the multi-slice processor is configured to carry out the steps of: determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor; responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions; and responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions. ### Claim 9 (depends on 8) The multi-slice processor of claim 8, wherein the operating condition comprises one of: a normal operating condition, a system hang condition, and a system recovery condition. ### Claim 10 (depends on 9) The multi-slice processor of claim 9, wherein determining the alternate issuance order is dependent upon both the change in the operating condition and the current issuance order. ### Claim 11 (depends on 10) The multi-slice processor of claim 10, wherein determining the alternate issuance order comprises: if the current issuance is out-of-order issuance and the operating condition is a system hang condition: determining the alternate issuance order to be in-order issuance; if the current issuance is out-of-order issuance and the operating condition is a system recovery condition: determining the alternate issuance order to be in-order issuance; if the current issuance is in-order issuance and a previous operating condition is a system hang condition: determining the alternate issuance order to be out-of-order issuance; and if the current issuance is in-order issuance and a previous operating condition is a system recovery condition: determining the alternate issuance order to be out-of-order issuance. ### Claim 12 (depends on 8) The multi-slice processor of claim 8, wherein the multi-slice processor comprises an issue queue and an instruction sequencing unit, and wherein the instruction sequencing unit includes an age array indicating relative ages of each instruction in an issue queue relative to each other instruction in the issue queue. ### Claim 13 (depends on 12) The multi-slice processor of claim 12, wherein each row of the age array corresponds to an entry in the issue queue, and wherein a first value at a particular row and a particular column indicates that the instruction in the issue queue corresponding to the particular row is younger than the instruction in the issue queue at the particular column. ### Claim 14 (depends on 13) The multi-slice processor of claim 13, wherein the multi-slice processor is further configured to carry out the steps of: responsive to the alternate issuance order being an in-order issuance order, determining, in dependence upon the age array, an in-order sequence for the plurality of instructions. ### Claim 15 An apparatus comprising: a plurality of execution slices, wherein the multi-slice processor is configured to carry out the steps of: determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor; responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions; and responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the operating condition comprises one of: a normal operating condition, a system hang condition, and a system recovery condition. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein determining the alternate issuance order is dependent upon both the change in the operating condition and the current issuance order. ### Claim 18 (depends on 16) The apparatus of claim 16, wherein determining the alternate issuance order comprises: if the current issuance is out-of-order issuance and the operating condition is a system hang condition: determining the alternate issuance order to be in-order issuance; if the current issuance is out-of-order issuance and the operating condition is a system recovery condition: determining the alternate issuance order to be in-order issuance; if the current issuance is in-order issuance and a previous operating condition is a system hang condition: determining the alternate issuance order to be out-of-order issuance; and if the current issuance is in-order issuance and a previous operating condition is a system recovery condition: determining the alternate issuance order to be out-of-order issuance. ### Claim 19 (depends on 15) The apparatus of claim 15, wherein the multi-slice processor comprises an issue queue and an instruction sequencing unit, and wherein the instruction sequencing unit includes an age array indicating relative ages of each instruction in an issue queue relative to each other instruction in the issue queue. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein each row of the age array corresponds to an entry in the issue queue, and wherein a first value at a particular row and a particular column indicates that the instruction in the issue queue corresponding to the particular row is younger than the instruction in the issue queue at the particular column.