# US 2017/0255459 A1 · Embedded device and program updating method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0255459 A1 - Document ID: US20170255459A1 - Status: Published application - Kind: A1 - Application number: 15/445,510 - Filed: 2017-02-28 - Published: 2017-09-07 - Earliest claimed: 2016-03-01 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Tadaaki TANIMOTO; Kesami HAGIWARA; Naoyuki MORITA - Web page: https://patentgrep.com/patent/US20170255459A1 ## CPC - G06F 8/65: Updates (security arrangements therefor G06F21/57) - G06F 8/654: using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories - G06F 8/658: Incremental updates; Differential updates - G06F 9/44521: {Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - H04L 67/34: {involving the movement of software or configuration parameters (network booting or remote initial program loading [RIPL] G06F9/4416)} - G06F 2212/251: Local memory within processor subsystem - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed. ## Claims ### Claim 1 An embedded device comprising: a network input/output unit receiving update information via a network; a first nonvolatile memory having a plurality of planes from/to which data can be read/written independently; a CPU executing a program disposed in the first nonvolatile memory; and a first address translator performing address translation by using an address translation table included in update information received by the network input/output unit, wherein in the first nonvolatile memory, a default program is disposed in a first plane and a differential program with respect to the default program, included in update information received by the network input/output unit is disposed in a second plane, wherein when an address obtained by decoding an instruction by the CPU is an address corresponding to a change part in the default program, the first address translator translates the address to an address in which the differential program is disposed, and wherein the CPU executes the differential program in accordance with the address translated by the first address translator. ### Claim 2 (depends on 1) The embedded device according to claim 1, wherein the number of planes of the first nonvolatile memory is three. ### Claim 3 (depends on 1) The embedded device according to claim 1, wherein the first address translator changes an upper bit sequence of predetermined number of bits in an address obtained by decoding an instruction by the CPU and couples the changed upper bit sequence and a lower bit sequence of the address, thereby translating the address to an address in which the differential program is disposed. ### Claim 4 (depends on 3) The embedded device according to claim 3, wherein when size of a differential code which replaces a code of a part to be substituted in the default program is larger than that of a code of the part to be substituted, or when the size of the code to be substituted or the size of the differential code is larger than segment size as size of a memory region corresponding to the predetermined number of bits, the first address translator translates a start address of the code of the part to be substituted to a predetermined address, and wherein the predetermined address is an address in which an instruction related to a jump instruction to a start address of an instruction sequence which replaces the code of the part to be substituted is stored. ### Claim 5 (depends on 1) The embedded device according to claim 1, further comprising: a second nonvolatile memory having a plurality of planes from/to which data can be read/written independently; and a second address translator performing address translation by using an address translation table included in update information received by the network input/output unit, wherein the CPU executes a program disposed in the first nonvolatile memory by using data disposed in the second nonvolatile memory, wherein in the second nonvolatile memory, default data is disposed in a first plane and differential data with respect to the default data, included in update information received by the network input/output unit is disposed in a second plane, wherein when an address obtained by decoding an instruction by the CPU is an address corresponding to a change part in the default data, the second address translator translates the address to an address in which the differential data is disposed, and wherein the CPU executes a process using the differential data in accordance with the address translated by the second address translator. ### Claim 6 (depends on 1) The embedded device according to claim 1, wherein the network input/output unit receives the update information including information constructing a program restoration point in addition to the differential program. ### Claim 7 (depends on 1) The embedded device according to claim 1, further comprising a signature verifying unit verifying signature of the update information, wherein when validity is confirmed by the signature verifying unit, the CPU executes the differential program. ### Claim 8 (depends on 5) The embedded device according to claim 5, wherein the second nonvolatile memory stores management information managing a write destination address when information included in the update information is written in the first nonvolatile memory or the second nonvolatile memory and erasure block number corresponding to the address, and wherein at the time of erasing information stored in the first nonvolatile memory or the second nonvolatile memory, a region designated by the erasure block number indicated in the management information is erased. ### Claim 9 (depends on 7) The embedded device according to claim 7, further comprising a control circuit which allows writing to the first nonvolatile memory of the update information when the update information is confirmed to be valid by the signature verifying unit. ### Claim 10 (depends on 1) The embedded device according to claim 1, wherein the network input/output unit receives update information excluding a part overlapped with update information already disposed in the first nonvolatile memory, and wherein the differential program obtained by eliminating the overlapped part is newly disposed in addition to the overlapped part already disposed in the first nonvolatile memory. ### Claim 11 (depends on 5) The embedded device according to claim 5, wherein the second nonvolatile memory stores management information managing a write destination address when information included in the update information is written in the first nonvolatile memory or the second nonvolatile memory and erasure block number corresponding to the address, and wherein when power supply stops at the time of writing the update infatuation to the first nonvolatile memory or the second nonvolatile memory or at the time of operation of applying the update information, after the power supply recovers, when the management information can be referred to, the update information written before the stop of the power supply is erased according to the management information. ### Claim 12 A program updating method comprising the steps of: receiving an address translation table and a differential program with respect to a default program; disposing the differential program in a second plane of a nonvolatile memory having a first plane in which the default program is disposed, the nonvolatile memory having a plurality of planes from/to which data can be independently read/written; when an address obtained by decoding an instruction is an address corresponding to a change part in the default program, translating the address to an address in which the differential program is disposed in accordance with the address translation table; and executing the differential program in accordance with the translated address.