# US 2017/0255406 A1 · Techniques for a Write Zero Operation

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- Number: US 2017/0255406 A1
- Document ID: US20170255406A1
- Status: Published application
- Kind: A1
- Application number: 15/277,182
- Filed: 2016-09-27
- Published: 2017-09-07
- Earliest claimed: 2016-03-04
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Shigeki Tomishima; Kuljit S. Bains
- Web page: https://patentgrep.com/patent/US20170255406A1

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/068: {Hybrid storage device}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1021: {Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 8/04: using a sequential addressing device, e.g. shift register, counter
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 16/20: Initialising; Data preset; Chip identification
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

## Claims

### Claim 1

An apparatus comprising:
a controller for a memory device that includes logic, at least a portion of which comprises hardware, the logic to:
forward a write 0 command to cause all bit values in a block of memory of the memory device to have a value of 0;
cause all global input/output (GIOs) to the block of memory to have a GIO value of 0; and
cause an internal activation of all column select lines (CSLs) to the block of memory by the memory device, the internal activation of all CSLs to cause the GIO value of 0 to be written to a first portion of the block of memory before a write line is internally activated by the memory device.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising the logic to:
cause all/GIOs to the block of memory to have value of 1 such that the internal activation of all CSLs to the block of memory cause the/GIO value of 1 to be written to a second portion of the block of memory before the write line is internally activated by the memory device.

### Claim 3 (depends on 1)

The apparatus of claim 1, the block of memory comprises a bank of the memory device.

### Claim 4 (depends on 1)

The apparatus of claim 1, comprising the memory device to include non-volatile memory or volatile memory, wherein the volatile memory includes dynamic random access memory (DRAM) and the non-volatile memory includes 3-dimensional cross-point memory, memory that uses chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, ovonic memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM).

### Claim 5 (depends on 1)

The apparatus of claim 1, comprising one or more of:
one or more processors coupled to the controller;
a network interface communicatively coupled to the apparatus;
a battery coupled to the apparatus; or
a display communicatively coupled to the apparatus.

### Claim 6

A method comprising:
forwarding, at a controller for a memory device, a write 0 command to cause all bit values in a block of memory of the memory device to have a value of 0;
causing all global input/output (GIOs) to the block of memory to have a GIO value of 0; and
causing an internal activation of all column select lines (CSLs) to the block of memory by the memory device, the internal activation of all CSLs to cause the GIO value of 0 to be written to a first portion of the block of memory before a write line is internally activated by the memory device.

### Claim 7 (depends on 6)

The method of claim 6, comprising:
causing all/GIOs to the block of memory to have value of 1 such that the internal activation of all CSLs to the block of memory cause the/GIO value of 1 to be written to a second portion of the block of memory before the write line is internally activated by the memory device.

### Claim 8 (depends on 6)

The method of claim 6, the block of memory comprising a bank of the memory device.

### Claim 9

An apparatus comprising:
a controller for a memory device that includes logic, at least a portion of which comprises hardware, the logic to:
forward a write 0 command to cause one or more blocks of memory for the memory device to store a value of 0; and
cause internal activation of column select lines (CSLs) to the one or more blocks of memory by the memory device, the internal activation of the CSLs to occur in a sequential manner until all columns of the one or more blocks of memory have been activated and the one or more blocks of memory store the value of 0.

### Claim 10 (depends on 9)

The apparatus of claim 9, comprising the logic to cause the internal activation of CSLs to occur in the sequential manner based on use of a column count of the internally activated CSLs by the memory device.

### Claim 11 (depends on 10)

The apparatus of claim 10, use of the column count to cause the internal activation of CSLs to occur in the sequential manner comprises the column count to cause sequential internal activation of CSLs to occur such that at least two CSLs are activated per iteration of the sequential internal activation of CSLs until all columns of the one or more blocks of memory have been activated and the one or more blocks of memory store the value of 0.

### Claim 12 (depends on 10)

The apparatus of claim 10, comprising the one or more blocks of memory includes a first block of memory and a second block of memory.

### Claim 13 (depends on 12)

The apparatus of claim 12, comprising the column count of the internally activated CSLs is based on:
a first column count to cause internal activation of CSLs to the first block of memory in the sequential manner until all columns of the first block of memory have been activated and the first block of memory stores the value of 0; and
a second column count, initiated after all columns of the first block of memory have been activated, to cause internal activation of CSLs to the second block of memory in the sequential manner until all columns of the second block of memory have been activated and the second block of memory stores the value of 0.

### Claim 14 (depends on 11)

The apparatus of claim 11, comprising the column count to cause internal activation of CSLs to the first and second blocks of memory by the memory device in the sequential manner such that columns of the first and second blocks of memory are activated substantially simultaneously in the sequential manner until all columns of the first and second blocks of memory have been activated and the first and second blocks of memory store the value of 0.

### Claim 15 (depends on 14)

The apparatus of claim 14, use of the column count to cause the internal activation of CSLs such that columns of the first and second blocks of memory are activated substantially simultaneously in the sequential manner further comprises sequential internal activation of CSLs to occur at the first and second blocks of memory such that at least two CSLs are activated substantially simultaneously at the first block of memory with at least two CSLs at the second block of memory per iteration of the sequential internal activation of CSLs.

### Claim 16 (depends on 9)

The apparatus of claim 9, the one or more block of memory comprising one or more banks of the memory device.

### Claim 17 (depends on 9)

The apparatus of claim 9, comprising the memory device to include non-volatile memory or volatile memory, wherein the volatile memory includes dynamic random access memory (DRAM) and the non-volatile memory includes 3-dimensional cross-point memory, memory that uses chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, ovonic memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM).

### Claim 18 (depends on 9)

The apparatus of claim 9, comprising one or more of:
one or more processors coupled to the controller;
a network interface communicatively coupled to the apparatus;
a battery coupled to the apparatus; or
a display communicatively coupled to the apparatus.

### Claim 19

A method comprising:
forwarding, at a controller for a memory device, a write 0 command to cause one or more blocks of memory for the memory device to store a value of 0; and
causing internal activation of column select lines (CSLs) to the one or more blocks of memory by the memory device, the internal activation of the CSLs to occur in a sequential manner until all columns of the one or more blocks of memory have been activated and the one or more blocks of memory store the value of 0.

### Claim 20 (depends on 19)

The method of claim 19, comprising causing the internal activation of CSLs to occur in the sequential manner based on use of a column count of the internally activated CSLs by the memory device.

### Claim 21 (depends on 20)

The method of claim 20, use of the column count to cause the internal activation of CSLs to occur in the sequential manner comprises the column count causing sequential internal activation of CSLs to occur such that at least two CSLs are activated per iteration of the sequential internal activation of CSLs until all columns of the one or more blocks of memory have been activated and the one or more blocks of memory store the value of 0.

### Claim 22 (depends on 20)

The method of claim 20, comprising the one or more blocks of memory includes a first block of memory and a second block of memory.

### Claim 23 (depends on 22)

The method of claim 22, comprising the column count of the internally activated CSLs is based on:
a first column count to cause internal activation of CSLs to the first block of memory in the sequential manner until all columns of the first block of memory have been activated and the first block of memory stores the value of 0; and
a second column count, initiated after all columns of the first block of memory have been activated, to cause internal activation of CSLs to the second block of memory in the sequential manner until all columns of the second block of memory have been activated and the second block of memory stores the value of 0.

### Claim 24 (depends on 21)

The method of claim 21, comprising the column count to cause internal activation of CSLs to the first and second blocks of memory by the memory device in the sequential manner such that columns of the first and second blocks of memory are activated substantially simultaneously in the sequential manner until all columns of the first and second blocks of memory have been activated and the first and second blocks of memory store the value of 0.

### Claim 25 (depends on 24)

The method of claim 24, use of the column count to cause the internal activation of CSLs such that columns of the first and second blocks of memory are activated substantially simultaneously in the sequential manner further comprises sequential internal activation of CSLs to occur at the first and second blocks of memory such that at least two CSLs are activated substantially simultaneously at the first block of memory with at least two CSLs at the second block of memory per iteration of the sequential internal activation of CSLs.