# US 2017/0255404 A1 · Techniques to Mirror a Command/Address or Interpret Command/Address Logic at a Memory Device

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- Number: US 2017/0255404 A1
- Document ID: US20170255404A1
- Status: Published application
- Kind: A1
- Application number: 15/266,991
- Filed: 2016-09-15
- Published: 2017-09-07
- Earliest claimed: 2016-03-05
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: George Vergis; Kuljit S. Bains; Bill Nale
- Web page: https://patentgrep.com/patent/US20170255404A1

## CPC

- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 13/4243: {with synchronous protocol}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/109: {Control signal input circuits}
- H10W 72/00: Interconnections or connectors in packages
- G06F 3/06: Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

## Claims

### Claim 1

An apparatus comprising:
circuitry for a memory device on first side of a dual in-line memory module (DIMM), the circuitry including logic, at least a portion of which comprises hardware, the logic to:
receive a command/address signal that indicates a first command/address to the target memory device;
determine based on a strap pin of the memory device that the first command/address indicated in the command/address signal is to be mirrored; and
mirror the first command/address to the memory device such that the first command/address indicated in the command/address signal is a mirror of a second command/address to a memory device on a second side of the DIMM.

### Claim 2 (depends on 1)

The apparatus of claim 1, the logic to mirror the first command/address to the target memory device comprises the logic to swap respective even numbered command/addresses to the target memory device with a respective next higher odd numbered command/addresses to the target memory device.

### Claim 3 (depends on 1)

The apparatus of claim 1, the logic to determine based on the strap pin that the first command/address indicated in the command/address signal is the mirror of the second command/address comprises the logic to determine that the strap pin is connected to a power pin of the target memory device.

### Claim 4 (depends on 3)

The apparatus of claim 3, the power pin comprises an output storage drain power voltage (VDDQ) pin.

### Claim 5 (depends on 1)

The apparatus of claim 1, the DIMM comprises a registered DIMM (RDIMM), a low power DIMM (LPDIMM), a load reduced DIMM (LRDIMM), a fully-buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM) or a small outline DIMM (SODIMM).

### Claim 6 (depends on 1)

The apparatus of claim 1, comprising the memory device to include non-volatile memory or volatile memory.

### Claim 7 (depends on 6)

The apparatus of claim 6, the volatile memory comprising dynamic random access memory (DRAM).

### Claim 8 (depends on 6)

The apparatus of claim 6, the non-volatile memory comprising 3-dimensional cross-point memory, memory that uses chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, ovonic memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM).

### Claim 9

A method comprising:
receiving, by circuitry at a target memory device on first side of a dual in-line memory module (DIMM), a command/address signal indicating a first command/address to the target memory device;
determining based on a strap pin of the target memory device that the first command/address indicated in the command/address signal is to be mirrored; and
mirroring the first command/address to the target memory device such that the first command/address indicated in the command/address signal is a mirror of a second command/address to a non-target memory device on a second side of the DIMM.

### Claim 10 (depends on 9)

The method of claim 9, mirroring the first command/address to the target memory device comprises swapping respective even numbered command/addresses to the target memory device with a respective next higher odd numbered command/addresses to the target memory device.

### Claim 11 (depends on 9)

The method of claim 9, determining based on the strap pin that the first command/address indicated in the command/address signal is the mirror of the second command/address comprises the strap pin being connected to a power pin of the target memory device.

### Claim 12 (depends on 11)

The method of claim 11, the power pin comprises an output storage drain power voltage (VDDQ) pin.

### Claim 13

An apparatus comprising:
circuitry for a memory device on a first side of a dual in line memory module (DIMM), the circuitry including logic, at least a portion of which comprises hardware, the logic to:
receive a command/address signal;
determine based on a strap pin of the memory device whether command/address logic indicated by the command/address signal has been inverted; and
interpret the command/address logic indicated by the command/address signal based on the determination.

### Claim 14 (depends on 13)

The apparatus of claim 13, comprising the logic to determine that the command/address signal indicates that the command/address logic has been inverted based on the strap pin being connected to a power pin of the target memory device.

### Claim 15 (depends on 14)

The apparatus of claim 14, the power pin comprises an output storage drain power voltage (VDDQ) pin.

### Claim 16 (depends on 14)

The apparatus of claim 14, comprising the command/address logic indicated by the command/address signal was inverted by circuitry for a register buffer of the DIMM.

### Claim 17 (depends on 14)

The apparatus of claim 14, the DIMM comprises a registered DIMM (RDIMM), a low power DIMM (LPDIMM), a load reduced DIMM (LRDIMM), a fully-buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM) or a small outline DIMM (SODIMM).

### Claim 18 (depends on 13)

The apparatus of claim 13, comprising the memory device to include non-volatile memory or volatile memory, the volatile memory including dynamic random access memory (DRAM), the non-volatile memory including 3-dimensional cross-point memory, memory that uses chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, ovonic memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM).

### Claim 19

A method comprising:
receiving, by circuitry a target memory device on a dual in-line memory module (DIMM), a command/address signal;
determining based on a strap pin of the memory device whether command/address logic indicated by the command/address signal has been inverted; and
interpreting the command/address logic indicated by the command/address signal based on the determination.

### Claim 20 (depends on 19)

The method of claim 19, comprising determining that the command/address signal indicates that the command/address logic has been inverted based on the strap pin being connected to a power pin of the target memory device.

### Claim 21 (depends on 20)

The method of claim 20, the power pin comprises an output storage drain power voltage (VDDQ) pin.

### Claim 22 (depends on 19)

The method of claim 19, comprising the command/address logic indicated by the command/address signal was inverted by circuitry for a register buffer of the DIMM.

### Claim 23

A system comprising:
a dual in-line memory module (DIMM) including one or more first memory devices on a first side and one or more second memory devices on a second side; and
a memory device from among the one or more first memory devices, the memory device having a first strap pin and including logic, at least a portion of which comprises hardware, the logic to:
receive a first command/address signal that indicates a first command/address targeted to the memory device;
determine whether the first strap pin is connected to a power pin; and
mirror the first command/address targeted to the memory device based on the determination such that the first command/address indicated in the first command/address signal is a mirror of a second command/address to a memory device from among the one or more second memory devices on the second side of the DIMM.

### Claim 24 (depends on 23)

The system of claim 23, to logic to mirror the first command/address to the memory device from among the first one or more memory devices comprises the logic to swap respective even numbered command/addresses to the memory device from among the first one or more memory devices with a respective next higher odd numbered command/addresses to the memory device from among the first one or more memory devices.

### Claim 25 (depends on 23)

The system of claim 23, the power pin comprises an output storage drain power voltage (VDDQ) pin.

### Claim 26 (depends on 23)

The system of claim 23, comprising the memory device from among the one or more first memory devices having a second strap pin and further including logic to:
receive a second command/address signal; and
interpret a command/address logic indicated by the second command/address signal based on the second strap pin being connected to a same or different power pin than what the first strap pin is connected to such that the command/address logic indicated by the second command/address signal is interpreted as being inverted.

### Claim 27 (depends on 26)

The system of claim 26, the same or different power pin than what the first strap pin is connected to comprises a same or different output storage drain power voltage (VDDQ) pin.

### Claim 28 (depends on 26)

The system of claim 26, comprising the command/address logic indicated by the second command/address signal was inverted by circuitry for a register buffer of the DIMM.

### Claim 29 (depends on 23)

The system of claim 23, the DIMM comprises a registered DIMM (RDIMM), a low power DIMM (LPDIMM), a load reduced DIMM (LRDIMM), a fully-buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM) or a small outline DIMM (SODIMM).

### Claim 30 (depends on 23)

The system of claim 23, comprising the memory device to include non-volatile memory or volatile memory, the volatile memory include dynamic random access memory (DRAM), the non-volatile memory including 3-dimensional cross-point memory, memory that uses chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, ovonic memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM).