# US 2017/0255394 A1 · Power saving techniques for memory systems

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- Number: US 2017/0255394 A1
- Document ID: US20170255394A1
- Status: Published application
- Kind: A1
- Application number: 15/448,327
- Filed: 2017-03-02
- Published: 2017-09-07
- Earliest claimed: 2016-03-03
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Jungwon Suh; Dexter Tamio Chun; Michael Hawjing Lo
- Web page: https://patentgrep.com/patent/US20170255394A1

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3225: of memory devices
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- G06F 13/1668: {Details of memory controller}
- G06F 13/1673: {using buffers}
- G06F 13/4234: {being a memory bus}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 2207/102: Compression or decompression of data before storage
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state. By reducing the amount of data that is transferred between a host and a memory element, power consumption is reduced.

## Claims

### Claim 1

A host processor comprising:
a physical layer (PHY) interface configured to be coupled to a plurality of data lanes of a memory bus; and
a memory controller coupled to the PHY interface, the memory controller comprising a data pattern checker logic circuit, wherein the memory controller is configured to:
use the data pattern checker logic circuit to determine if patterns of repeatable data exist in data to be written to a memory element over the memory bus; and
consolidate the data into fewer lanes and send the data across only certain ones of the plurality of data lanes of the memory bus.

### Claim 2 (depends on 1)

The host processor of claim 1, wherein the memory controller further comprises a look-up table and the memory controller writes to the look-up table address information for data written to the memory element.

### Claim 3 (depends on 2)

The host processor of claim 2, wherein the memory controller is configured to use the look-up table to determine if data being read from the memory element has the patterns of repeatable data such that a consolidated read command may be used.

### Claim 4 (depends on 1)

The host processor of claim 1, further comprising a read data copy register associated with the PHY interface, wherein the read data copy register is configured to duplicate read data.

### Claim 5 (depends on 1)

The host processor of claim 1, wherein the memory controller is configured to consolidate duplicated data from eight lanes onto one data lane.

### Claim 6 (depends on 1)

The host processor of claim 1, wherein the memory controller is configured to consolidate duplicated data from eight lanes onto two or four data lanes.

### Claim 7 (depends on 1)

The host processor of claim 1, wherein the PHY interface comprises a backchannel lane.

### Claim 8 (depends on 7)

The host processor of claim 7, wherein the memory controller is configured to receive an indication that data from the memory controller will be consolidated data.

### Claim 9 (depends on 1)

The host processor of claim 1 integrated into an integrated circuit (IC).

### Claim 10

A memory system comprising:
an input/output (JO) block configured to be coupled to a memory bus;
a memory bank comprising memory elements, the memory bank communicatively coupled to the JO block; and
a write register operative to receive data from the memory bus through the JO block and duplicate the data a number of times according to a command from a host processor.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the memory bank is configured to store the duplicated data from the write register in the memory elements.

### Claim 12 (depends on 10)

The memory system of claim 10, further comprising a data pattern checker logic circuit associated with the memory bank.

### Claim 13 (depends on 12)

The memory system of claim 12, wherein the data pattern checker logic circuit is configured to determine if patterns of repeatable data exist in data read from the memory elements and consolidate the data into fewer lanes and send the data across only certain ones of a plurality of data lanes of the memory bus.

### Claim 14 (depends on 10)

The memory system of claim 10, further comprising a backchannel lane output.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein the memory system is configured to send an indication of duplicated data to the host processor over a backchannel lane through the backchannel lane output.

### Claim 16

A host processor comprising:
a physical layer (PHY) interface configured to be coupled to a plurality of data lanes of a memory bus;
a read register; and
a memory controller coupled to the PHY interface, wherein the memory controller is configured to:
receive data through the PHY interface from a memory system; and
cause data within the read register to be duplicated based on information received from the memory system.

### Claim 17 (depends on 16)

The host processor of claim 16, wherein the memory controller is configured to receive an indication that data received from the memory system in response to a read command will be consolidated data.

### Claim 18 (depends on 16)

The host processor of claim 16, wherein the memory controller causes the data within the read register to be duplicated based on information received through a backchannel lane of the memory bus.

### Claim 19

A memory system comprising:
an input/output (JO) block configured to be coupled to a memory bus; and
a memory bank comprising memory elements, the memory bank communicatively coupled to the IO block, the memory bank configured to respond to a read command by sending consolidated data over the memory bus to a host processor.

### Claim 20 (depends on 19)

The memory system of claim 19, further comprising a backchannel output configured to provide information to the host processor indicating that the consolidated data is being sent responsive to the read command.

### Claim 21 (depends on 19)

The memory system of claim 19, further comprising a data pattern checker logic circuit associated with the memory bank.

### Claim 22 (depends on 21)

The memory system of claim 21, wherein the data pattern checker logic circuit is configured to check data being sent to the host processor for repetitions that are consolidated into the consolidated data.

### Claim 23 (depends on 19)

The memory system of claim 19, wherein the memory system is configured to send an indication of consolidated data being sent to the host processor.

### Claim 24

An apparatus comprising:
a host processor comprising a memory controller and a physical layer (PHY) interface;
a memory system; and
a memory bus, wherein the host processor sends data to be written into the memory system via the PHY interface and the memory bus, and
wherein the memory controller comprises a data pattern checker logic circuit, and is operative to:
use the data pattern checker logic circuit to determine if patterns of repeatable data exist in the data to be written to into the memory system over the memory bus; and
consolidate the data to reduce data sent over the memory bus.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the memory controller further comprises a look-up table and the memory controller writes to the look-up table address information for data written into the memory system.

### Claim 26 (depends on 24)

The apparatus of claim 24, wherein the memory controller is configured to consolidate duplicated data from eight lanes onto one data lane, two data lanes, or four data lanes.

### Claim 27 (depends on 24)

The apparatus of claim 24, wherein the memory controller is further operative to provide an indication to the memory system that the data sent over the memory bus will be consolidated data.

### Claim 28 (depends on 24)

The apparatus of claim 24 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

### Claim 29

An apparatus comprising:
a host processor comprising a memory controller and a physical layer (PHY) interface;
a memory system; and
a memory bus, wherein the host processor receives data read from the memory system via the PHY interface and the memory bus, and
wherein the memory system is operative to determine if patterns of repeatable data exist in the data being read from the memory system and consolidate the data to reduce data sent over the memory bus in response to a read command from the host processor.

### Claim 30 (depends on 29)

The apparatus of claim 29, further comprising a backchannel lane through which the memory system sends information to the host processor indicating that the consolidated data is being sent responsive to the read command.

### Claim 31 (depends on 29)

The apparatus of claim 29, wherein the memory system further comprises a data pattern checker logic circuit.

### Claim 32 (depends on 31)

The apparatus of claim 31, wherein the data pattern checker logic circuit checks data being sent to the host processor for repetitions that are consolidated into the consolidated data.

### Claim 33 (depends on 29)

The apparatus of claim 29, wherein the memory system sends an indication of consolidated data being sent to the host processor.