# US 2017/0255385 A1 · Nonvolatile semiconductor memory device

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- Number: US 2017/0255385 A1
- Document ID: US20170255385A1
- Status: Published application
- Kind: A1
- Application number: 15/331,606
- Filed: 2016-10-21
- Published: 2017-09-07
- Earliest claimed: 2016-03-02
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Naoya TOKIWA
- Web page: https://patentgrep.com/patent/US20170255385A1

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 3/061: {Improving I/O performance}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 7/067: {Single-ended amplifiers}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 11/34: using semiconductor devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A nonvolatile semiconductor memory device includes a memory cell array. The memory cells of the memory cell array can be programmed to have different threshold voltages. A word line is connected to the memory cells. A controller is configured to receive a first command and perform a first read sequence and a second read sequence to read data from the memory cell array. In the first read sequence, a series of different voltage levels are applied to the word line and data is read from the array at each voltage level. In the second read sequence, a read voltage level is set based on the data obtained during the first read sequence. The read voltage level is applied to the word line to read the data to be output from the memory cell array.

## Claims

### Claim 1

A nonvolatile semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells, each of which can be programmed to have a different threshold voltage;
a word line connected to the plurality of memory cells; and
a controller configured to receive a first command and to perform a first read sequence and a second read sequence to read data to be output from the memory cell array, wherein
in the first read sequence, a series of different voltage levels are applied to the word line to read data from the memory cell array at each different voltage level, and
in the second read sequence, a read voltage level set based on the data read from the memory cell array during the first read sequence is applied to the word line to read the data to be output from the memory cell array in response to the first command.

### Claim 2 (depends on 1)

The device according to claim 1, wherein a read target address is supplied with the first command, and a number of bits read from the memory cell array at each of the different voltage levels in the series is less than a number bits corresponding to the read target address.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the controller is further configured to:
compare a read result at a first voltage level in the series to a read result at a second voltage level in the series and to calculate a first difference result from the comparison,
compare the read result at the second voltage level to a read result at a third voltage level in the series and to calculate a second difference result from the comparison, and
set the read voltage level using the first and second difference results.

### Claim 4 (depends on 3)

The device according to claim 3, wherein the controller is configured to set the read level voltage according to a comparison between the first difference result and a reference value and a comparison between the second difference result and the reference value.

### Claim 5 (depends on 4)

The device according to claim 4, further comprising:
a first register in which a result of the comparison between the first difference result and the reference value can be stored; and
a second register in which a result of the comparison between the second difference result and the reference value can be stored, wherein
the controller causes the output of information stored in the first and second registers in response to a second command.

### Claim 6 (depends on 5)

The device according to claim 5, wherein the read level voltage is calculated outside of the controller, and a value of the read level voltage is supplied to the controller with a third command.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the read level voltage is equal to one of the voltage levels in the series of different voltage levels.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the read level voltage is between two voltage levels that are adjacent to each other in the series of different voltage levels.

### Claim 9 (depends on 1)

The device of according to claim 1, wherein the controller is configured to calculate the read level voltage.

### Claim 10 (depends on 1)

The device according to claim 1, wherein the read level voltage is calculated outside of the controller.

### Claim 11

A nonvolatile semiconductor memory device, comprising:
a memory cell array that includes a plurality of memory cells, each of which can programmed to have one of a first threshold voltage and a second threshold voltage;
a word line connected to the plurality of memory cells; and
a controller configured to:
perform a first read sequence comprising applying a series of different voltage levels to the word line to read data from the memory cell array at each different voltage level and storing the data read from the memory cell array in a cache, and
perform a second read sequence comprising applying a read level voltage to the word line and reading data stored in the memory cell array at a target address and outputting the data from the target address, wherein
the read level voltage is set based on the data read from memory cell array in the first read sequence.

### Claim 12 (depends on 11)

The device according to claim 11, the controller performs the first read sequence and the second read sequence in response to a first command accompanied by the target address.

### Claim 13 (depends on 11)

The device according to claim 11, wherein the controller performs the first read sequence in response to a first command, outputs the data stored in the cache in response to a second command, and performs the second read sequence in response to a third command accompanied by a value for the read level voltage.

### Claim 14 (depends on 11)

The device of according to claim 11, wherein the controller is configured to calculate the read level voltage.

### Claim 15 (depends on 11)

The device according to claim 11, wherein the read level voltage is calculated outside of the controller.

### Claim 16 (depends on 11)

The device according to claim 11, wherein the controller is further configured to:
compare a read result at a first voltage level in the series to a read result at a second voltage level in the series to calculate a first difference result,
compare the read result at the second voltage level to a read result at a third voltage level in the series to calculate a second difference result, and
set the read voltage level using the first and second difference results.

### Claim 17 (depends on 11)

The device according to claim 11, wherein the read level voltage is between two voltage levels that are adjacent to each other in the series of different voltage levels.

### Claim 18

A NAND-type memory device, comprising:
a memory cell array including memory cells in which data can be stored by programming a threshold voltage for one of more memory cells in the memory cell array; and
a controller configured to:
perform an optimum value search read on at least a portion of the memory cell array, the optimum value search read including data read operations on at least the portion of the memory cell at a series of different voltage levels, and
perform an optimum value read on at least a targeted portion of the memory cell array, the optimum value read including a data read operation at a read voltage level set according to results from the data read operations in the optimum value search read.

### Claim 19 (depends on 18)

The NAND-type memory device of claim 18, wherein the controller is further configured to calculate the read voltage level using results from the data read operations in the optimum value search read.

### Claim 20 (depends on 18)

The NAND-type memory device of claim 18, wherein the controller is configured to perform the optimum value search read in response to a first command, to output the results from the data read operations in the optimum value search read in response to a second command, and to perform the optimum value read in response to a third command accompanied by a calculated value for the read voltage level for the optimum value read.