# US 2017/0255246 A1 · Reducing Power by Vacating Subsets of CPUs and Memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0255246 A1 - Document ID: US20170255246A1 - Status: Published application - Kind: A1 - Application number: 15/600,474 - Filed: 2017-05-19 - Published: 2017-09-07 - Earliest claimed: 2015-05-08 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Vishal SHARDA; Bruce Lee WORTHINGTON - Web page: https://patentgrep.com/patent/US20170255246A1 ## CPC - G06F 1/3234: Power saving characterised by the action undertaken - G06F 1/32: Means for saving power - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics. ## Claims ### Claim 1 In a computing environment, a method of allocating resources to one or more power regions, the method comprising: identifying one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state, wherein the one or more primary power regions comprise one or more processors including functionality to handle hardware interrupts, and attached memory; identifying one or more secondary power regions that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state; identifying at least one hardware device for which an interrupt for the hardware device should be assigned to a processor at a primary power region, based on hardware device characteristics; and assigning an interrupt for the at least one hardware device to a processor at an identified primary power region. ### Claim 2 (depends on 1) The method of claim 1, further comprising bringing a secondary power region back from a limited state; allocating at least one interrupt to the secondary power region brought back from a limited state. ### Claim 3 (depends on 2) The method of claim 2, wherein bringing a secondary power region back from a limited state comprises bringing the secondary power regions back from a limited state based on an anticipated future need for additional computing resources. ### Claim 4 (depends on 1) The method of claim 1, further comprising moving one or more interrupts from a secondary power region and then moving the secondary power region to a limited state. ### Claim 5 (depends on 1) The method of claim 1, further comprising allocating at least one interrupt to a primary or secondary power region based on load-balancing criteria. ### Claim 6 (depends on 1) The method of claim 1, further comprising allocating at least one interrupt to a primary or secondary power region to group related threads or related memory. ### Claim 7 (depends on 1) The method of claim 1, further comprising allocating at least one interrupt based on the at least one interrupt changing from a movable resource to an unmovable resource. ### Claim 8 (depends on 1) The method of claim 1, further comprising allocating at least one interrupt to a secondary power region based on the at least one interrupt changing from an unmovable resource to a movable resource. ### Claim 9 (depends on 1) The method of claim 1, further comprising allocating one or more interrupts to both a primary power region and one or more secondary power regions. ### Claim 10 (depends on 1) The method of claim 1, wherein one or more of the power regions comprises a package. ### Claim 11 In a computing environment, a system for allocating resources to one or more power regions, the system comprising: one or more computer processors, wherein the one or more computer processors are configured to implement: a power region determination identifier configured to identify one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state and to identify one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state; a resource allocator configured to: identify whether interrupts should be allocated to a primary power region or a secondary power region based on interrupt characteristics; and to allocate interrupts, to primary or secondary power regions as identified. ### Claim 12 (depends on 11) The system of claim 11, further comprising a power region activator configured to bring a secondary power region back from a limited state. ### Claim 13 (depends on 12) The system of claim 12 wherein the power region activator is configured to bring a secondary power region back from a limited state based on an anticipated future need for additional computing resources. ### Claim 14 (depends on 12) The system of claim 12 wherein the resource allocator is configured to move one or more interrupts from a secondary power region and the power region activator is configured to move the secondary power region to a limited state. ### Claim 15 (depends on 12) The system of claim 12 wherein the resource allocator is configured to allocate at least one interrupt to a primary or secondary power region based on load-balancing criteria. ### Claim 16 (depends on 12) The system of claim 12 wherein the resource allocator is configured to allocate at least one interrupt to a primary or secondary power region to group related threads or related memory. ### Claim 17 (depends on 12) The system of claim 12 wherein the resource allocator is configured to allocate at least one interrupt based on the at least one interrupt changing from a movable resource to an unmovable resource or from an unmovable resource to a movable resource. ### Claim 18 (depends on 12) The system of claim 12 wherein the resource allocator is configured to allocate one or more interrupts to both a primary power region and one or more secondary power regions. ### Claim 19 In a computing environment, a system comprising: one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state; one or more secondary power regions that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state; and at least one interrupt allocated to one of the primary power regions, based on interrupt characteristics. ### Claim 20 (depends on 19) The system of claim 19, wherein one or more of the power regions comprises a package.