# US 2017/0255238 A1 · Memory device and host device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0255238 A1 - Document ID: US20170255238A1 - Status: Published application - Kind: A1 - Application number: 15/254,609 - Filed: 2016-09-01 - Published: 2017-09-07 - Earliest claimed: 2016-03-07 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Yoshiyuki NAKADA - Web page: https://patentgrep.com/patent/US20170255238A1 ## CPC - G06F 1/24: Resetting means - G06F 3/0605: {by facilitating the interaction with a user or administrator} - G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0689: {Disk arrays, e.g. RAID, JBOD} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one embodiment, a memory device includes a memory and a controller circuit. The memory holds first data and second data. The first data and the second data are results of monitoring state of the memory device. The first data and the second data include values indicating results of monitoring attributes common between these data. The values are updated according to operation status of the memory device. The controller circuit switches an object to be read from the memory between the first data and the second data. ## Claims ### Claim 1 A memory device comprising: a memory to hold first data and second data that are results of monitoring state of the memory device, the first data and the second data including values indicating results of monitoring attributes common between these data, the values being updated according to operation status of the memory device; and a controller circuit that switches an object to be read from the memory between the first data and the second data. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein access information is registered in the memory device, and the controller circuit, according to a read request, reads data designated based on the access information out of the first data and the second data. ### Claim 3 (depends on 2) The memory device according to claim 2, wherein the controller circuit receives a first command that is a request to register access information and a second command that is a read request. ### Claim 4 (depends on 2) The memory device according to claim 2, wherein the controller circuit receives a command that is a read request including an instruction to register access information. ### Claim 5 (depends on 2) The memory device according to claim 2, wherein the memory holds a plurality of second data, the plurality of second data includes values indicating results of monitoring attributes common between these data, and access information that designates one of the first data and the plurality of second data is registered in the memory device. ### Claim 6 (depends on 1) The memory device according to claim 1, wherein access information is registered in the memory device, and the controller circuit, according to a reset request, resets second data designated based on the access information. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein if access information designating the first data is registered, the controller circuit prohibits resetting according to the reset request. ### Claim 8 (depends on 6) The memory device according to claim 6, wherein the controller circuit receives a first command that is a request to register access information and a second command that is a reset request. ### Claim 9 (depends on 6) The memory device according to claim 6, wherein the controller circuit receives a command that is a reset request including an instruction to register access information. ### Claim 10 (depends on 6) The memory device according to claim 6, wherein the memory holds a plurality of second data, the plurality of second data include values indicating results of monitoring attributes common between these data, and access information that designates one of the plurality of second data is registered in the memory device. ### Claim 11 A memory device comprising: a memory to hold first data and second data that are results of monitoring state of the memory device, the first data and the second data including values indicating results of monitoring attributes common between these data, the values being updated according to operation status of the memory device; and a controller circuit that disables resetting the first data according to a request and resets the second data according to a request. ### Claim 12 A host device which is connectable to a memory device that holds first data and second data that are results of monitoring state of the memory device, the first data and the second data including values indicating results of monitoring attributes common between these data, the values being updated according to operation status of the memory device, the host device comprising: a controller circuit that issues requests to read the first data and the second data and reads either the first data or the second data based on access information registered in the memory device. ### Claim 13 (depends on 12) The host device according to claim 12, wherein the controller circuit issues a read request and receives data designated based on the access information out of the first data and the second data. ### Claim 14 (depends on 13) The host device according to claim 13, wherein the controller circuit issues a first command that is a request to register access information and a second command that is a read request. ### Claim 15 (depends on 13) The host device according to claim 13, wherein the controller circuit issues a command that is a read request including an instruction to register access information. ### Claim 16 (depends on 12) The host device according to claim 12, wherein the controller circuit issues a request to register access information that designates one of the first data and a plurality of second data, and the plurality of second data includes values indicating results of monitoring attributes common between these data. ### Claim 17 (depends on 12) The host device according to claim 12, wherein the controller circuit issues a reset request so as to have memory device reset second data designated based on the access information registered in the memory device. ### Claim 18 (depends on 17) The host device according to claim 17, wherein if access information designating the first data is registered in the memory device, the memory device resetting according to the reset request is prohibited. ### Claim 19 (depends on 17) The host device according to claim 17, wherein the controller circuit issues a first command that is a request to register access information and a second command that is a reset request. ### Claim 20 (depends on 17) The host device according to claim 17, wherein the controller circuit issues a command that is a reset request including an instruction to register access information.