# US 2017/0255223 A1 · Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure Automotive Applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0255223 A1 - Document ID: US20170255223A1 - Status: Published application - Kind: A1 - Application number: 15/059,341 - Filed: 2016-03-03 - Published: 2017-09-07 - Earliest claimed: 2016-03-03 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Virendra Bansal; Rahul Gulati; Palkesh Jain; Roberto Avanzi - Web page: https://patentgrep.com/patent/US20170255223A1 ## CPC - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - G01R 31/31922: {Timing generation or clock distribution (G01R31/3191 takes precedence)} - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - H03K 3/037: Bistable circuits - H03K 5/14: by the use of delay lines (H03K5/133 takes precedence) - H03K 2005/00058: {controlled by a digital setting} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks. ## Claims ### Claim 1 A clock monitoring circuit, comprising: a plurality of cascaded flops in which a clock input of each flop is the same as a clock to be monitored, a data input of each flop is driven by a divided version of the clock being monitored so that the data input to each of the plurality of cascaded flops is delayed relative to other cascaded flops via one or more programmable delay elements; an encoder coupled to outputs of the cascaded flops and configured to generate an encoded output value that represents the outputs of the cascaded flops; a comparator configured to generate and store an interrupt when the encoded output value does not match a programmed value; and an error correction code generator configured to generate and store an error correction code for each stored interrupt. ### Claim 2 (depends on 1) The clock monitoring circuit of claim 1, wherein the plurality of cascaded flops and programmable delay elements are included in a clock monitoring component and configured so that the clock to be monitored is evaluated at least once in every fault tolerant time interval (FTTI). ### Claim 3 (depends on 1) The clock monitoring circuit of claim 1, wherein the clock to be monitored is a clock that is included in a control system of a vehicle. ### Claim 4 (depends on 1) The clock monitoring circuit of claim 1, wherein the clock to be monitored is a clock that is included in a system on chip (SOC) configured to control an operation of an Advanced Driver Assistance System (ADAS) when included in a motor vehicle. ### Claim 5 (depends on 1) The clock monitoring circuit of claim 1, further comprising a built-in self-test selector component coupled to a system clock and the clock to be monitored. ### Claim 6 (depends on 1) The clock monitoring circuit of claim 1, wherein the error correction code generator is configured to generate the error correction code in response to determining that the interrupt has been stored in a status register. ### Claim 7 (depends on 6) The clock monitoring circuit of claim 6, wherein the error correction code generator is further configured to generate a second error correction code in response to determining that information has been written to a configuration register. ### Claim 8 (depends on 1) The clock monitoring circuit of claim 1, further comprising a manager component configured to generate an error signal based on the interrupt and the error correction code. ### Claim 9 (depends on 1) The clock monitoring circuit of claim 1, further comprising a manager component configured to determine whether the clock to be monitored is operating correctly without the use of a reference clock. ### Claim 10 A method of monitoring a clock with a circuit monitoring component, comprising: configuring the clock to be monitored; configuring plurality of delay elements in the circuit monitoring component; clearing a plurality of flops in the circuit monitoring component; passing a clock pulse from the clock through the plurality of delay elements and the plurality of flops and waiting until the plurality of flops in the circuit monitoring component are loaded; encoding loaded flop values to generate an encoded value; determining whether the encoded value matches a programmed value; and generating an interrupt in response to determining that the encoded value matches does not match the programmed value. ### Claim 11 (depends on 10) The method of claim 10, further comprising: repeating operations of clearing the plurality of flops, passing the clock pulse through the plurality of delay elements and the plurality of flops, encoding the loaded flop values and determining whether the encoded value matches the programmed value in response to determining that the encoded value matches does not match the programmed value. ### Claim 12 (depends on 10) The method of claim 10, further comprising: determining whether a power-on self test is enabled; and performing a self test in response to determining that the power-on self test is enabled. ### Claim 13 (depends on 12) The method of claim 12, wherein performing a self test comprises: configuring an expected count; clearing the plurality flops in the circuit monitoring component; generating a clock pulse circuit monitoring component and waiting until the plurality of flops are loaded; encoding loaded flop values to generate an encoded value; determining whether the encoded value matches the expected count and whether an interrupt has been asserted; and determining that the self test is complete and failed in response to determining that the encoded value matches the expected count and an interrupt has been asserted; and determining that the self test is complete and passed in response to determining that the encoded value does not match the expected count or that an interrupt has not been asserted. ### Claim 14 (depends on 10) The method of claim 10, further comprising: determining whether the clock to be monitored is operating correctly without the use of a reference clock. ### Claim 15 (depends on 10) The method of claim 10, further comprising: generating an error correction code in response to determining that the interrupt has been stored in a status register. ### Claim 16 A clock monitoring circuit, comprising: a plurality of flops; a plurality of delay elements, each of which is coupled to one of the plurality of flops; means for configuring a clock to be monitored; means for configuring the plurality of delay elements; means for clearing the plurality of flops; means for passing a clock pulse from the clock through the plurality of delay elements and the plurality of flops and waiting until the plurality of flops are loaded; means for encoding loaded flop values to generate an encoded value; means for determining whether the encoded value matches a programmed value; and means for generating an interrupt in response to determining that the encoded value matches does not match the programmed value. ### Claim 17 (depends on 16) The clock monitoring circuit of claim 16, further comprising: means for repeating operations of clearing the plurality of flops, passing the clock pulse through the plurality of delay elements and the plurality of flops, encoding loaded flop values and determining whether the encoded value matches the programmed value in response to determining that the encoded value matches does not match the programmed value. ### Claim 18 (depends on 16) The clock monitoring circuit of claim 16, further comprising: means for determining whether a power-on self test is enabled; and means for performing a self test in response to determining that the power-on self test is enabled. ### Claim 19 (depends on 18) The clock monitoring circuit of claim 18, wherein means for performing a self test comprises: means for configuring an expected count; means for clearing the plurality flops; means for generating a clock pulse circuit monitoring component and waiting until the plurality of flops are loaded; means for encoding loaded flop values to generate an encoded value; means for determining whether the encoded value matches the expected count and whether an interrupt has been asserted; and means for determining that the self test is complete and failed in response to determining that the encoded value matches the expected count and an interrupt has been asserted; and means for determining that the self test is complete and passed in response to determining that the encoded value does not match the expected count or that an interrupt has not been asserted. ### Claim 20 (depends on 16) The clock monitoring circuit of claim 16, further comprising: means for determining whether the clock to be monitored is operating correctly without the use of a reference clock. ### Claim 21 (depends on 16) The clock monitoring circuit of claim 16, further comprising: means for generating an error correction code in response to determining that the interrupt has been stored in a status register. ### Claim 22 A system on chip, comprising: a clock to be monitored; and a clock monitoring circuit coupled to the clock to be monitored, wherein the clock monitoring circuit comprises: a plurality of cascaded flops in which a clock input of each flop is the same as the clock to be monitored, a data input of each flop is driven by a divided version of the clock being monitored so that a data input to each of the plurality of cascaded flops is delayed relative to other cascaded flops via one or more programmable delay elements; an encoder coupled to outputs of the cascaded flops and configured to generate an encoded output value that represents the outputs of the cascaded flops; a comparator configured to generate and store an interrupt when the encoded output value does not match a programmed value; and an error correction code generator configured to generate and store an error correction code for each stored interrupt. ### Claim 23 (depends on 22) The system on chip of claim 22, wherein the plurality of cascaded flops and programmable delay elements are configured so that the clock to be monitored is evaluated at least once in every fault tolerant time interval (FTTI). ### Claim 24 (depends on 22) The system on chip of claim 22, wherein the clock to be monitored is a clock that is configured to be included in a control system of a vehicle. ### Claim 25 (depends on 22) The system on chip of claim 22, wherein the clock to be monitored is a clock configured to be used to control an operation of an Advanced Driver Assistance System (ADAS) included in a motor vehicle. ### Claim 26 (depends on 22) The system on chip of claim 22, further comprising a system clock, wherein the clock monitoring circuit further comprises a built-in self-test selector component that is coupled to the system clock and to the clock to be monitored. ### Claim 27 (depends on 22) The system on chip of claim 22, wherein the error correction code generator is configured to generate the error correction code in response to determining that the interrupt has been stored in a status register. ### Claim 28 (depends on 27) The system on chip of claim 27, wherein the error correction code generator is further configured to generate a second error correction code in response to determining that information has been written to a configuration register. ### Claim 29 (depends on 22) The system on chip of claim 22, wherein the clock monitoring circuit further comprises a manager component configured to generate an error signal based on the interrupt and the error correction code. ### Claim 30 (depends on 22) The system on chip of claim 22, wherein the clock monitoring circuit further comprises a manager component configured to determine whether the clock to be monitored is operating correctly without the use of another clock in the system on chip.