# US 2017/0254871 A1 · Calibration of Inverting Amplifier Based Impedance Analyzers

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- Number: US 2017/0254871 A1
- Document ID: US20170254871A1
- Status: Published application
- Kind: A1
- Application number: 15/445,762
- Filed: 2017-02-28
- Published: 2017-09-07
- Earliest claimed: 2016-03-01
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Charles Kasimer Sestok, IV
- Web page: https://patentgrep.com/patent/US20170254871A1

## CPC

- G01R 35/005: {Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence)}
- G01R 27/14: Measuring resistance by measuring current or voltage obtained from a reference source (G01R27/16, G01R27/20, G01R27/22 take precedence)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A circuit for measuring an impedance of a device under test (DUT). The circuit includes: (i) circuitry for generating a stimulus wave at a stimulus frequency; (ii) an amplifier circuit coupled to the DUT to present a response signal from the DUT in response to the stimulus wave; (iii) switching circuitry for selectively coupling, between the stimulus wave and an input to the amplifier, either the DUT, a first calibration impedance, or a second calibration impedance. With the switching functionality, calibrations are performed so to provide a measure of impedance of the DUT in response to the plural calibrations.

## Claims

### Claim 1

A circuit for measuring an impedance of a device under test (DUT), comprising:
circuitry for generating a stimulus wave at a stimulus frequency;
an amplifier circuit coupled to the DUT to present a response signal from the DUT in response to the stimulus wave;
switching circuitry for selectively coupling, between the stimulus wave and an input to the amplifier, either the DUT, a first calibration impedance, or a second calibration impedance; and
processor circuitry programmed to sample a signal responsive to the response signal, wherein the processor is programmed to:
in a first iteration, with the switching circuitry selectively coupling the first calibration impedance between the stimulus wave and an input to the amplifier, sampling a first signal responsive to the response signal;
in a second iteration, with the switching circuitry selectively coupling the second calibration impedance between the stimulus wave and an input to the amplifier, sampling a second signal responsive to the response signal;
in a third iteration, with the switching circuitry selectively coupling the DUT between the stimulus wave and an input to the amplifier, sampling a third signal responsive to the response signal; and
wherein the processor circuitry is further programmed to provide a measure of impedance of the DUT in response to the first signal responsive to the response signal, the second signal responsive to the response signal, and the third signal responsive to the response signal.

### Claim 2 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 and further comprising an analog-to-digital converter (ADC) for sampling the response signal.

### Claim 3 (depends on 2)

The circuit for measuring an impedance of DUT of claim 2 wherein the processor circuitry is coupled to an output of the ADC.

### Claim 4 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the processor circuitry is further programmed to control the switching circuitry.

### Claim 5 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the processor circuitry is further programmed to provide a measure of impedance of the DUT in response to a multiplier and an offset determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 6 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the processor circuitry is further programmed to provide a measure of impedance of the DUT in response to a multiplier determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 7 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the processor circuitry is further programmed to provide a measure of impedance of the DUT in response to an offset determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 8 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the circuitry for generating a stimulus wave comprises circuitry for generating a sinusoidal stimulus wave.

### Claim 9 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the circuitry for generating a stimulus wave comprises circuitry for generating a non-sinusoidal stimulus wave.

### Claim 10 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1 wherein the circuitry for generating a stimulus wave comprises circuitry for generating a square wave stimulus wave.

### Claim 11 (depends on 10)

The circuit for measuring an impedance of DUT of claim 10 and further comprising an anti-aliasing filter coupled between the circuitry for generating a stimulus wave and the DUT.

### Claim 12 (depends on 1)

The circuit for measuring an impedance of DUT of claim 1:
and further comprising a reference impedance; and
wherein the processor circuitry is further programmed to provide a measure of impedance of the DUT in response to a multiplier and an offset determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 13 (depends on 12)

The circuit for measuring an impedance of DUT of claim 12:
wherein the multiplier comprises a representation of a transconductance of the amplifier and the reference impedance; and
wherein the offset comprises a model of degradation of a virtual ground of the amplifier.

### Claim 14

A method of measuring an impedance of a device under test (DUT), comprising:
generating a stimulus wave at a stimulus frequency;
coupling a signal responsive to the stimulus wave to a first terminal of the DUT;
selectively coupling, between the stimulus wave and an input to an amplifier, either the DUT, a first calibration impedance, or a second calibration impedance, to present a response signal from the selective coupling in response to the stimulus wave; and
performing the steps of:
in a first iteration, coupling the first calibration impedance between the stimulus wave and an input to the amplifier and sampling a first signal responsive to the response signal;
in a second iteration, coupling the second calibration impedance between the stimulus wave and an input to the amplifier and sampling a second signal responsive to the response signal;
in a third iteration, coupling the DUT between the stimulus wave and an input to the amplifier and sampling a third signal responsive to the response signal; and
providing a measure of impedance of the DUT in response to the first signal responsive to the response signal, the second signal responsive to the response signal, and the third signal responsive to the response signal.

### Claim 15 (depends on 14)

The method of claim 14 wherein the providing step is for providing the a measure of impedance of the DUT in response to a multiplier and an offset determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 16 (depends on 14)

The method of claim 14 wherein the providing step is for providing a measure of impedance of the DUT in response to a multiplier determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 17 (depends on 14)

The method of claim 14 wherein the providing step is for providing a measure of impedance of the DUT in response to an offset determined from the first signal responsive to the response signal and the second signal responsive to the response signal.

### Claim 18 (depends on 14)

The circuit for measuring an impedance of DUT of claim 14 wherein the step of generating a stimulus wave comprises generating a sinusoidal stimulus wave.

### Claim 19 (depends on 14)

The circuit for measuring an impedance of DUT of claim 14 wherein the step of generating a stimulus wave comprises generating a non-sinusoidal stimulus wave.

### Claim 20 (depends on 14)

The circuit for measuring an impedance of DUT of claim 14 wherein the step of generating a stimulus wave comprises generating a square stimulus wave.