# US 2017/0254844 A1 · Impedance Analyzer Using Square Wave Stimuli

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- Number: US 2017/0254844 A1
- Document ID: US20170254844A1
- Status: Published application
- Kind: A1
- Application number: 15/344,565
- Filed: 2016-11-06
- Published: 2017-09-07
- Earliest claimed: 2016-03-01
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Charles Kasimer Sestok, IV
- Web page: https://patentgrep.com/patent/US20170254844A1

## CPC

- G01R 27/28: Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response (in line transmission systems H04B3/46)
- G01R 27/14: Measuring resistance by measuring current or voltage obtained from a reference source (G01R27/16, G01R27/20, G01R27/22 take precedence)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A microcontroller-based system for measuring the impedance of a device under test (DUT) (35) responsive to a square wave stimulus. A clock generator circuit (26) in the microcontroller (20) generates a clock signal at a base clock frequency. A first timer (25) divides down the base clock frequency by a first frequency divisor integer to set the stimulus frequency of a square wave generated by a general purpose input/output (GPIO) function (24), and a second timer (28) divides down the base clock frequency by a second frequency divisor integer to set the sampling frequency of an analog-to-digital converter (ADC) (30). A discrete Fourier transform executed by a processor (22) is used to determine the impedance of the DUT at the stimulus frequency. The first and second integers are selected so that aliased harmonics fall in different DFT bins from the fundamental tone.

## Claims

### Claim 1

A circuit for measuring an impedance of a device under test (DUT), comprising:
clock circuitry generating a base clock signal;
a driver circuit for generating a square wave stimulus at stimulus frequency having a period corresponding to a first integer number of cycles of the base clock signal;
an anti-aliasing filter coupled to the DUT, for filtering the stimulus to remove high frequencies;
an amplifier circuit coupled to the DUT to present a response signal from the DUT in response to the filtered stimulus;
an analog-to-digital converter (ADC) for sampling the response signal at a sample frequency having a period corresponding to a second integer number of cycles of the base clock signal; and
processor circuitry coupled to the ADC, programmed to execute a discrete Fourier transform on the sampled response signal, using a window of samples numbering an integer multiple of a separation number defined by the first integer divided by the greatest common divisor of the first and second integers.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising:
a first timer for counting a number of cycles of the base clock signal corresponding to the first integer; and
a second timer for counting a number of cycles of the base clock signal corresponding to the second integer;
wherein the driver circuit issues the square wave stimulus responsive to the first timer counting the first integer number of cycles of the base clock signal;
and wherein the ADC samples the response signal responsive to the second timer counting the second integer number of cycles of the base clock signal.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the clock circuitry, the first and second timers, the driver circuit, the ADC, and the processor circuitry are implemented within a single integrated circuit.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the separation number is odd.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the separation number is even and not divisible by four.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the first and second integers are relatively prime.

### Claim 7 (depends on 1)

The circuit of claim 1, further comprising:
a calibration impedance;
a plurality of switches for selectably coupling one of the calibration impedance and the DUT to the anti-aliasing filter and the amplifier circuit.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the amplifier circuit comprises:
an operational amplifier having a non-inverting input coupled to a voltage source, an inverting input coupled to the DUT, and an output coupled to the ADC; and
a reference impedance coupled between the output and the inverting input of the operational amplifier.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the reference impedance is a variable impedance comprising:
a plurality of impedances; and
switches for selectably coupling one or more of the impedances between the output and the inverting input of the operational amplifier.

### Claim 10 (depends on 1)

The circuit of claim 1, wherein the processor circuitry is programmed to sequentially select a plurality of values of the first integer, each value corresponding to a different stimulus frequency;
and wherein the processor circuitry is programmed to select a value for the second integer responsive to the selected value of the first integer.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein the processor circuitry is programmed to select a value for the second integer so that the frequency of the base clock signal divided by the second integer is less than a maximum sampling frequency of the ADC.

### Claim 12 (depends on 1)

The circuit of claim 1, wherein the processor circuitry is further programmed to calculate the impedance of the DUT responsive to a magnitude and phase result of the DFT at a selected DFT bin corresponding to the stimulus frequency.

### Claim 13

A method of measuring an impedance of a device under test (DUT), comprising:
generating a base clock signal at a base clock frequency;
selecting a first target frequency of a stimulus signal;
selecting a first frequency divisor integer so that the base clock frequency divided by the first frequency divisor integer is near the first target frequency;
selecting a second frequency divisor integer;
applying, to the DUT, a square wave stimulus signal at a stimulus frequency corresponding to the base clock frequency divided by the first frequency divisor integer;
sampling a response signal corresponding to the response of the DUT to the square wave stimulus signal, at a sampling frequency corresponding to the base clock frequency divided by the second frequency divisor integer, to produce a sample stream;
computing a discrete Fourier transform (DFT) on a DFT window having a number of samples that is an integer multiple of a separation number defined as the first frequency divisor integer divided by the greatest common divisor of the first and second frequency divisor integers; and
determining the impedance of the DUT from a magnitude and phase results of the DFT at a selected bin corresponding to the stimulus frequency.

### Claim 14 (depends on 13)

The method of claim 13, wherein the step of applying the square wave stimulus signal comprises:
counting a number of cycles of the base clock signal; and
generating the stimulus signal responsive to the counting step reaching a number of cycles corresponding to the first frequency divisor integer; and
wherein the step of sampling the response signal comprises:
counting a number of cycles of the base clock signal; and
controlling an analog-to-digital converter to sample the response signal responsive to the counting step reaching a number of cycles corresponding to the second frequency divisor integer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the step of selecting the second frequency divisor integer comprises:
selecting a value of the second frequency divisor integer so that the base clock frequency divided by the second frequency divisor integer is less than a maximum sample rate of the analog-to-digital converter.

### Claim 16 (depends on 13)

The method of claim 13, wherein the separation number is odd-numbered.

### Claim 17 (depends on 13)

The method of claim 13, wherein the separation number is even and not divisible by four.

### Claim 18 (depends on 13)

The method of claim 13, wherein the first and second frequency divisor integers are relatively prime.

### Claim 19 (depends on 13)

The method of claim 13, further comprising:
then selecting a second target frequency; and
then repeating the selecting, applying, sampling, computing, and determining steps.