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US 2017/0250699 A1Published application
Capacitor Order Determination in An Analog-to-Digital Converter
AssigneeTexas Instruments Deutschland GmbH
InventorsThomas Fuchs, Rudiger Kuhn, Bernhard Wolfgang Ruck
Life of this patent
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Abstract
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.
Claims18
A method, comprising:
- measuring an error value for each of a plurality of capacitors in a digital-to-analog (DAC) capacitor array of an analog-to-digital converter (ADC);
- determining an order of the plurality of capacitors based on the measured error values;
- and
- programming the ADC to use the plurality of capacitors in the determined order during conversions of analog signals to digital codes.
1 more element
A system, comprising:
- a processor;
- a digital-to-analog converter (DAC) coupled to the processor and configured to provide analog signals to an analog-to-digital converter (ADC);
- storage coupled to the processor and containing executable code that, when executed by the processor, causes the processor to:
- measure an error value for each of a plurality of capacitors in a DAC capacitor array of the ADC;
- determine an order of the plurality of capacitors based on the measured error values;
- and
- program the ADC to use the plurality of capacitors in the determined order during conversions of analog signals to digital codes.
4 more elements
An analog-to-digital converter (ADC), comprising:
- a comparator configured to receive an analog input signal;
- a successive approximation register (SAR) coupled to an output of the comparator and configured to generate an intermediate binary digital code;
- a digital-to-analog converter (DAC) capacitor array coupled to an input of the comparator and including a plurality of most significant bit (MSB) capacitors, wherein each MSB capacitor is coupled to a corresponding switch that includes a control input and each switch is configurable to couple a terminal of the corresponding capacitor to a reference voltage;
- a binary-to-thermometric decoder coupled to the SAR and configured to convert the intermediate binary digital code from the SAR to a thermometric digital code;
- and
- a switch matrix coupled to the MSB capacitor switches and to the binary-to-thermometric decoder, wherein the switch matrix is configurable to couple any bit of the thermometric digital code to a control input of any of the MSB capacitor switches.
3 more elements
Dependencies are inferred from the claim text.