Semiconductor device and pll circuit
AssigneeRenesas Electronics Corporation
InventorsAtsushi MOTOZAWA, Yoshitaka HIRAI
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AssigneeRenesas Electronics Corporation
InventorsAtsushi MOTOZAWA, Yoshitaka HIRAI
Estimating the term…
An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.
A semiconductor device comprising a phase locked loop circuit, wherein the phase locked loop circuit comprises:
Dependencies are inferred from the claim text.