Back to results
US 2017/0250680 A1Published application
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorRoh YAMAMOTO
Life of this patent
Estimating the term…
Abstract
A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.
Claims27
A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a first circuit;
- a second circuit;
- a first inverter circuit;
- a first constant current circuit;
- and
- a second constant current circuit,
- wherein the second transistor comprises a gate and a back gate,
- wherein each of the first transistor and the second transistor is an n-channel transistor,
- wherein the third transistor is a p-channel transistor,
- wherein the first circuit has a first terminal, a second terminal, and a third terminal,
- wherein the first circuit is configured to output a potential corresponding to current flowing through the first terminal and current flowing through the second terminal from the third terminal,
- wherein the second circuit has a fourth terminal and a fifth terminal,
- wherein the second circuit is configured to output one of two potentials from the fifth terminal in accordance with a potential applied to the fourth terminal,
- wherein the first constant current circuit is configured to make constant current flow from an input terminal of the first constant current circuit to an output terminal of the first constant current circuit,
- wherein the second constant current circuit is configured to make constant current flow from an input terminal of the second constant current circuit to an output terminal of the second constant current circuit,
- wherein one of a source and a drain of the first transistor is electrically connected to the first terminal,
- wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the first constant current circuit,
- wherein one of a source and a drain of the second transistor is electrically connected to the second terminal,
- wherein the other of the source and the drain of the second transistor is electrically connected to the input terminal of the first constant current circuit,
- wherein a gate of the third transistor is electrically connected to the third terminal,
- wherein one of a source and a drain of the third transistor is electrically connected to the input terminal of the second constant current circuit,
- wherein an input terminal of the first inverter circuit is electrically connected to the one of the source and the drain of the third transistor,
- wherein an output terminal of the first inverter circuit is electrically connected to the fourth terminal, and
- wherein the fifth terminal is electrically connected to the back gate of the second transistor.
24 more elements
A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a first circuit;
- a first inverter circuit;
- a first constant current circuit;
- and
- a second constant current circuit,
- wherein the second transistor comprises a gate and a back gate,
- wherein each of the first transistor and the second transistor is an n-channel transistor,
- wherein the third transistor is a p-channel transistor,
- wherein the first circuit has a first terminal, a second terminal, and a third terminal,
- wherein the first circuit is configured to output a potential corresponding to current flowing through the first terminal and current flowing through the second terminal from the third terminal,
- wherein the first constant current circuit is configured to make constant current flow from an input terminal of the first constant current circuit to an output terminal of the first constant current circuit,
- wherein the second constant current circuit is configured to make constant current flow from an input terminal of the second constant current circuit to an output terminal of the second constant current circuit,
- wherein one of a source and a drain of the first transistor is electrically connected to the first terminal,
- wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the first constant current circuit,
- wherein one of a source and a drain of the second transistor is electrically connected to the second terminal,
- wherein the other of the source and the drain of the second transistor is electrically connected to the input terminal of the first constant current circuit,
- wherein a gate of the third transistor is electrically connected to the third terminal,
- wherein one of a source and a drain of the third transistor is electrically connected to the input terminal of the second constant current circuit,
- wherein an input terminal of the first inverter circuit is electrically connected to the one of the source and the drain of the third transistor, and
- wherein the back gate of the second transistor is electrically connected to the one of the source and the drain of the third transistor.
20 more elements
A semiconductor device comprising:
- a comparator having a first input terminal, a second input terminal, and an output terminal,
- wherein the comparator comprises a first transistor comprising a first gate and a second gate between which a semiconductor layer is positioned,
- wherein the first gate is electrically connected to one of the first input terminal and the second input terminal,
- wherein the comparator is configured to output any of a first signal and a second signal in accordance with signals input to the first input terminal and the second input terminal, and
- wherein the second gate is configured to be input with a first potential when the first signal is output from the comparator and be input with a second potential when the second signal is output from the comparator.
2 more elements
Dependencies are inferred from the claim text.