Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in rram devices

A resistive random access memory device, comprising:

• a first electrode;
• a resistive random access memory oxide layer disposed over the first electrode;
• an oxide layer disposed over the resistive random access memory oxide layer;
• wherein the oxide layer has a recess region at a center portion extending to a top portion of the resistive random access memory oxide layer;
• and
• a second electrode disposed over the oxide layer.

A computing device, comprising:

• a motherboard;
• a processor mounted on the motherboard;
• and
• a communication chip fabricated on the same chip as the processor or mounted on the motherboard;
• wherein the processor comprises:
• a substrate;
• a first electrode disposed over the substrate;
• a second electrode disposed over the first electrode;
• and
• a resistive random access memory oxide layer disposed between the first electrode and the second electrode;
• wherein the resistive random access memory oxide layer has a recess at the interface between the second electrode and the resistive random access memory oxide layer.