Memory Device and Method for Fabricating the Same

A method comprising:

• forming a nanowire over a substrate;
• applying a plurality of doping processes to the nanowire to form a first drain/source region at a lower portion of the nanowire, a second drain/source region at an upper portion of the nanowire and a channel region between the first drain/source region and the second drain/source region;
• depositing a first dielectric layer over the substrate;
• depositing a first gate dielectric layer along sidewalls of the channel region and over the first dielectric layer;
• depositing a control gate layer over the first dielectric layer, wherein a top surface the control gate layer is lower than a top surface of the channel region;
• depositing a second gate dielectric layer along the sidewalls of the channel region and over the control gate layer;
• and
• forming a ring-shaped floating gate region surrounding an upper portion of the channel region.

A method comprising:

• patterning a substrate to form a nanowire over a substrate;
• forming a first drain/source region at a lower portion of the nanowire using a first doping process;
• forming a second drain/source region at an upper portion of the nanowire using a second doping process;
• forming a channel region using a third doping process, wherein the channel region is between the first drain/source region and the second drain/source region;
• forming a control gate region surrounding a lower portion of the channel region;
• and
• forming a floating gate region surrounding an upper portion of the channel region.