# US 2017/0250253 A1 · Semiconductor device with buried conductive region, and method for manufacturing the semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0250253 A1
- Document ID: US20170250253A1
- Status: Published application
- Kind: A1
- Application number: 15/250,638
- Filed: 2016-08-29
- Published: 2017-08-31
- Earliest claimed: 2016-02-25
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics S.R.L.
- Inventors: Fabrizio Fausto Renzo Toia; Claudio Contiero; Elisabetta Pizzi; Simone Dario Mariani
- Web page: https://patentgrep.com/patent/US20170250253A1

## CPC

- H10D 62/378: {Contact regions to the substrate regions}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/01: Manufacture or treatment
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/278: {Pendeoepitaxy}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/38: {characterised by treatments done after the formation of the materials}
- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10W 15/00: Highly-doped buried regions of integrated devices
- H10W 15/01: {Manufacture or treatment}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device comprising: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor body including an active region that houses an electronic component;
a dielectric passive region positioned on opposite sides of the active region;
a conductive buried region, of metallic material, which extends in the semiconductor body adjacent to said active region; and
a metallic contact that extends between the conductive buried region and a top surface of the semiconductor body and forms a path for electrical access to the conductive buried region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive buried region and the metallic contact are made of a same metallic material, and form a continuous path.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive buried region includes:
a barrier layer in direct contact with said semiconductor body, and
a metallic filling layer which extends on the barrier layer, wherein the barrier layer is configured to form a barrier against diffusion of metallic species from the metallic filling layer to the semiconductor body.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive buried region further extends at said passive region, and wherein the passive region includes an insulating region which forms a field oxide, said metallic contact extending in the passive region through the insulating region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein said electronic component is chosen in the group consisting of: a bipolar transistor, a CMOS transistor, a DMOS transistor, a VDMOS transistor, and a trench-MOS transistor.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein said semiconductor body includes:
a substrate having a first conductivity type;
an implanted region having a second type of conductivity, implanted in the substrate; and
an epitaxial layer, having the second type of conductivity, which extends over the substrate,
wherein the conductive buried region extends within the implanted region and/or in the epitaxial layer, in such a way to be separated from a lower portion of the substrate by a portion of the implanted region.

### Claim 7

A method for manufacturing an electronic device, comprising:
forming a buried cavity in a semiconductor body;
forming an active region, including an electronic component, in the semiconductor body above the buried cavity;
forming a passive region, surrounding the active region, in the semiconductor body;
etching selective portions of the semiconductor body at the passive region to form one or more openings in fluidic connection with the buried cavity;
depositing metallic material within the buried cavity through the one or more openings, completely coating internal walls of the buried cavity and forming a metallic buried region, and completely coating internal walls of the one or more openings to form one or more paths for electrical access to the conductive buried region.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the depositing includes depositing the metallic material using CVD and/or ALD technology.

### Claim 9 (depends on 7)

The method according to claim 7, further comprising, prior to depositing the metallic material, depositing a barrier layer configured to form a barrier against diffusion of metallic species towards the semiconductor body and to form an ohmic contact with the substrate.

### Claim 10 (depends on 7)

The method according to claim 7, wherein coating the internal walls of the buried cavity and of coating the internal walls of the one or more openings are carried out simultaneously.

### Claim 11 (depends on 7)

The method according to claim 7, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, forming the buried cavity including:
digging trenches in the substrate, said trenches defining walls of semiconductor material between them;
growing epitaxially, in a deoxidizing environment, starting from the walls, a closing layer of semiconductor material designed to close said trenches at tops of the trenches; and
carrying out a thermal treatment that causes migration of the semiconductor material of said walls and forms a single buried cavity.

### Claim 12 (depends on 7)

The method according to claim 7, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, forming the buried cavity including:
digging trenches in the substrate, said trenches defining walls of semiconductor material between them; and
carrying out a thermal treatment in a deoxidizing environment, at a temperature comprised between 1050° C. and 1250° C., at a pressure of 5-50 Torr, for a time of 5-20 min, which causes migration of the semiconductor material of said walls which closes the trenches at tops of the trenches and forms a single buried cavity.

### Claim 13 (depends on 7)

The method according to claim 7, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, forming the buried cavity including:
digging selective portions of the substrate and forming a recess;
filling the recess with silicon germanium to form a sacrificial layer of silicon germanium;
growing an epitaxial layer on the substrate and on the sacrificial layer; and
removing completely the sacrificial layer through said one or more openings.

### Claim 14 (depends on 11)

The method according to claim 11, wherein the semiconductor body includes a substrate and an epitaxial layer formed on the substrate, wherein the substrate has a first conductivity, the method further comprising:
implanting dopant species that have a second conductivity type in the substrate, thereby forming an implanted region; and
forming the buried cavity inside the implanted region and/or the epitaxial layer so that the conductive buried region is separated from a portion of the substrate by a portion of the implanted region and/or of the epitaxial layer.

### Claim 15

A semiconductor device comprising:
a semiconductor body including an active region and a buried aperture below the active region;
an electronic component in the active region;
a conductive buried region, of metallic material, which coats internal walls of the buried aperture in the semiconductor body; and
a metallic contact extending between the conductive buried region and a top surface of the semiconductor body and forms a path for electrical access to the conductive buried region.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the conductive buried region and the metallic contact are made of a same metallic material, and form a continuous path.

### Claim 17 (depends on 15)

The semiconductor device according to claim 15, wherein the conductive buried region includes:
a barrier layer in direct contact with said semiconductor body, and
a metallic filling layer which extends on the barrier layer, wherein the barrier layer is configured to form a barrier against diffusion of metallic species from the metallic filling layer to the semiconductor body.

### Claim 18 (depends on 15)

The semiconductor device according to claim 15, further comprising:
a dielectric passive region defining opposite sides of the active region, wherein the conductive buried region further extends below said passive region and the metallic contact extending through the passive region.

### Claim 19 (depends on 15)

The semiconductor device according to claim 15, wherein said electronic component is chosen in the group consisting of: a bipolar transistor, a CMOS transistor, a DMOS transistor, a VDMOS transistor, and a trench-MOS transistor.

### Claim 20 (depends on 15)

The semiconductor device according to claim 15, wherein said semiconductor body includes:
a substrate having a first conductivity type;
an implanted region having a second type of conductivity, implanted in the substrate; and
an epitaxial layer, having the second type of conductivity, which extends over the substrate,
wherein the conductive buried region extends within the implanted region and/or in the epitaxial layer, in such a way to be separated from a lower portion of the substrate by a portion of the implanted region.