Variable resistance memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsZhe WU, Soon-Oh PARK, Jeong-HEE PARK, Dong-Ho AHN, Hideki HORII
Life of this patent
Estimating the term…
Abstract
A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.
Claims22
A variable resistance memory device, comprising:
- a selection pattern;
- an intermediate electrode contacting a first surface of the selection pattern;
- a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern;
- and
- a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.
11-12. (canceled)
A variable resistance memory device, comprising:
- a selection pattern including an ovonic threshold switch (OTS) material;
- an intermediate electrode contacting a first surface of the selection pattern;
- a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern;
- and
- a first electrode contacting a second surface of the selection pattern and including a conductive material having a work function of greater than about 4 eV, the second surface of the selection pattern being opposite the first surface thereof.
18-40. (canceled)
A variable resistance memory device, comprising:
- a selection pattern;
- a variable resistance pattern;
- an intermediate electrode between the selection pattern and the variable resistance pattern;
- an outer layer on the selection pattern such that the selection pattern is between the outer layer and the intermediate electrode, the outer layer contacting a surface of the selection pattern,
- wherein the variable resistance memory device includes a P-N junction or a Schottky barrier at an interface between the outer layer and the selection pattern.
Dependencies are inferred from the claim text.