Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method

An integrated circuit transistor, comprising:

• an upper semiconductor layer separated by a cavity from a lower semiconductor layer;
• an epitaxial layer on said upper semiconductor layer and including an opening extending through said epitaxial layer to provide, from said epitaxial layer, a source epitaxial region on one side of said opening and a drain epitaxial region on an opposite side of said opening;
• a transistor source region comprising a combination of said source epitaxial region and a first portion of the upper semiconductor layer underlying the source epitaxial region together as a single crystal region that extends to said cavity;
• a transistor drain region comprising a combination of said drain epitaxial region and a second portion of the upper semiconductor layer underlying the drain epitaxial region together as a single crystal region that extends to said cavity;
• wherein a third portion of the upper semiconductor layer between transistor source and drain regions forms a transistor channel region;
• and
• a transistor gate electrode in said opening above the transistor channel region.

An integrated circuit transistor, comprising:

• a semiconductor layer including an active region;
• an epitaxial layer of semiconductor material on said semiconductor layer;
• a dielectric layer on said epitaxial layer;
• an opening extending through said dielectric layer and said epitaxial layer of semiconductor material to provide:
• a transistor source region formed from a combination of a source epitaxial region on one side of said opening and a first portion of the semiconductor layer underlying the source epitaxial region together as a single crystal region;
• and
• a transistor drain region formed from a combination of a drain epitaxial region on opposite side of said opening and a second portion of the semiconductor layer underlying the drain epitaxial region together as a single crystal region;
• wherein a third portion of the semiconductor layer between transistor source and drain regions forms a transistor channel region;
• sidewall spacers on side walls of said opening adjacent the dielectric layer wherein a bottom-most surface of said sidewall spacers is in contact with a top surface of the transistor source and drain regions;
• a transistor gate electrode in said opening;
• and
• a dielectric layer in said opening and insulating the transistor gate electrode from the transistor source and drain regions.

An integrated circuit transistor, comprising:

• a semiconductor layer including an active region;
• an epitaxial layer of semiconductor material on said semiconductor layer and including an opening extending through said epitaxial layer of semiconductor material to provide:
• a transistor source region formed from a combination of a source epitaxial region on one side of said opening and a first portion of the semiconductor layer underlying the source epitaxial region together as a single crystal region;
• and
• a transistor drain region formed from a combination of a drain epitaxial region on opposite side of said opening and a second portion of the semiconductor layer underlying the drain epitaxial region together as a single crystal region;
• wherein a third portion of the semiconductor layer between transistor source and drain regions forms a transistor channel region;
• sidewall spacers on side walls of said opening;
• a transistor gate electrode in said opening and insulated in a lateral direction from the transistor source and drain regions by at least the sidewall spacers;
• and
• a dielectric layer at a bottom of said opening, said transistor gate electrode insulated in a vertical direction from the transistor source and drain regions and the transistor channel region solely by said dielectric layer at the bottom of said opening, said vertical direction being perpendicular to the lateral direction.