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US 2017/0250197 A1Published application
Layout structure for semiconductor integrated circuit
AssigneeSocionext Inc.
InventorHiroyuki SHIMBO
Life of this patent
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Abstract
In a circuit block, a plurality of standard cells are arranged to form a circuit of silicon-on-insulator (SOI) transistors. Also arranged in the circuit block is a capacitor cell including a capacitor arranged between a power supply line for supplying VDD and a power supply line for supplying VSS. An antenna cell, including an antenna diode formed between either of the two power supply lines and either a substrate or a well, is arranged adjacent to the capacitor cell.
Claims5
A layout structure for a semiconductor integrated circuit including silicon-on-insulator (SOI) transistors, the structure comprising:
- a circuit block in which a plurality of standard cells are arranged, thereby forming a circuit of the SOI transistors, wherein
- the circuit block includes a capacitor cell including a capacitor arranged between a first power supply line for supplying a supply potential and a second power supply line for supplying a ground potential, and
- the capacitor cell includes an antenna diode formed between either the first or second power supply line and either a substrate or a well, or
- an antenna cell, including an antenna diode formed between either the first or second power supply line and either the substrate or the well, is arranged adjacent to the capacitor cell.
1 more element
Dependencies are inferred from the claim text.