Silicon controlled rectifier (scr) based esd protection device

A method for forming a device comprising:

• providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer, the surface substrate is defined with a device region for accommodating an electrostatic discharge (ESD) protection device;
• and
• forming an ESD protection device in the device region, wherein forming the ESD protection device comprising
• forming an ESD protection device isolation region surrounding the device region in the surface substrate, wherein the ESD protection device isolation region is a device shallow trench isolation (STI) region, the device STI region isolates the device region from other device regions and extends completely through the surface substrate to the buried insulator layer,
• forming a first well and a second well in the surface substrate, wherein the first well comprises first polarity type dopants and defines a part of a first portion (FP) and the second well comprises second polarity type dopants and defines a part of a second portion (SP) of the ESD protection device, wherein first sides of the first and second wells in a y-direction abut,
• forming a first internal isolation region in the FP and a second internal isolation region in the SP, the first internal isolation region defines a second side of the first well along the y-direction and the second internal isolation region defines a second side of the SP along the y-direction, wherein the first and second internal isolation regions are internal STI regions which extend partially into the surface substrate, leaving a portion of the first and second wells between the first and second internal isolation regions and the buried insulator layer, and wherein
• a first FP contact region is disposed between the first internal device isolation region and the first side of the first device well, the first FP contact region is part of the first well, and
• a first SP contact region is disposed between the second internal device isolation region and the first side of the second well, the first SP contact region is part of the second well, and
• forming second FP and SP contact regions in the device region, wherein
• the second FP contact region is disposed between the device isolation region and the first internal isolation region, the second FP contact region comprises second polarity type dopants and extends a complete thickness of the surface substrate, a lower portion of the second FP contact region abuts the first well below the first internal isolation region,
• the second SP contact region is disposed between the device isolation region and the second internal isolation region, the second SP contact region comprises first polarity type dopants and extends the complete thickness of the surface substrate, a lower portion of the second FP contact region abuts the second well below the second internal isolation region, and
• the second SP contact region and the first and second wells form a first junction transistor while the second FP contact region and the first and second wells form a second junction transistor of the ESD protection device.