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US 2017/0250170 A1Published application
Integrated circuit package and methods of forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
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Abstract
An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.
Claims20
A package-on-package (PoP) device comprising:
- a logic chip having an active side and a back side, the back side being opposite the active side, the active side comprising a plurality of conductive posts;
- a first molding compound encircling the logic chip;
- a plurality of through-molding vias (TMVs) adjacent the logic chip, extending through the first molding compound, and attached to one or more first redistribution layers (RDLs), wherein the one or more first RDLs are disposed under the first molding compound and the logic chip, the back side of the logic chip facing the one or more first RDLs;
- one or more second RDLs over the logic chip and the first molding compound, the active side of the logic chip facing the one or more second RDLs, wherein the plurality of TMVs extend from the one or more first RDLs to the one or more second RDLs, and wherein an entirety of the TMVs are disposed in the first molding compound;
- and
- a memory chip over the one or more second RDLs, the memory chip having an active side and a back side, the back side being opposite the active side, the active side comprising a first plurality of conductive connectors coupled to the one or more second RDLs, the active side of the memory chip facing the one or more second RDLs, the one or more second RDLs being interposed between the active sides of the memory chip and the logic chip, wherein the one or more second RDLs electrically connects the memory chip to the logic chip and the plurality of TMVs.
3 more elements
A method comprising:
- forming a first package structure, wherein forming the first package structure comprises:
- bonding a logic chip to a memory chip, wherein the logic chip comprises a first plurality of contact pads;
- attaching a first plurality of pre-formed conductive studs to the first plurality of contact pads;
- dispensing a first molding compound over the logic chip between the memory chip and each of the first plurality of pre-formed conductive studs;
- bonding the first package structure to a package substrate, wherein the package substrate comprises a second plurality of contact pads;
- attaching a second plurality of pre-formed conductive studs to the second plurality of contact pads;
- and
- dispensing a second molding compound over the package substrate between the first package structure and each of the second plurality of pre-formed conductive studs.
5 more elements
A structure comprising:
- a first redistribution structure comprising a one or more conductive lines and vias in one or more insulating layers;
- a logic chip over the first redistribution structure, the logic chip having an active side and a back side, the active side comprising a plurality of contact pads, the back side of the logic chip facing the first redistribution structure;
- a first molding compound over the first redistribution structure and encircling the logic chip;
- a plurality of electrical connectors adjacent the logic chip and extending through the first molding compound;
- a second redistribution structure over the active side of the logic chip, the first molding compound, and the plurality of electrical connectors, the second redistribution structure comprising one or more conductive lines and vias in one or more insulating layers, the plurality of electrical connectors being electrically connected to the first redistribution structure and the second redistribution structure;
- and
- a memory chip over the second redistribution structure, the memory chip having an active side and a back side, the active side facing the second redistribution structure and comprising a first plurality of conductive connectors coupled to the second redistribution structure.
4 more elements
Dependencies are inferred from the claim text.