Semiconductor package assembly

A semiconductor package assembly, comprising:

• a system-on-chip (SOC) package, comprising:
• a first semiconductor die;
• and
• a molding compound surrounding the first semiconductor die, being in contact with the first semiconductor die;
• and
• a first memory package stacked on the SOC package, comprising:
• a first memory die without through silicon via (TSV) interconnects formed passing therethrough,
• wherein the SOC package comprises a first redistribution layer (RDL) structure for the first semiconductor die coupled thereto, and wherein the first memory package comprises a second redistribution layer (RDL) structure for the first memory die coupled thereto,
• wherein the SOC package further comprises an additional semiconductor die coupled to the first semiconductor die,
• wherein the additional semiconductor die has through silicon via (TSV) interconnects formed through the additional semiconductor die,
• wherein the additional semiconductor die is disposed between the first semiconductor die and the first RDL structure.

A semiconductor package assembly, comprising:

• a first package, comprising:
• a first semiconductor die;
• and
• a first redistribution layer (RDL) structure for the first semiconductor die coupled thereto;
• and
• a second package stacked on the first package, comprising:
• a first memory die and a second memory die without through silicon via (TSV) interconnects formed passing therethrough,
• a second redistribution layer (RDL) structure for the first memory die and the second memory die coupled thereto,
• wherein the first memory die and the second memory die are disposed side-by-side on the second RDL structure.