US 2017/0250116 A1Published application

Semiconductor device having dual channels, complementary semiconductor device and manufacturing method thereof

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsYi-Chung Lin, Chen-Chieh Chiang, Chi-Cherng Jeng

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Abstract

Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.

Claims20

Dependent claims

A semiconductor device having dual channels, comprising:

a first portion and a second portion, sharing a buried gate pillar extending from a first surface of a substrate toward a second surface opposite to the first surface, wherein:
the first portion is embedded into a substrate and further comprises:
a first gate dielectric layer, located between a first sidewall of the buried gate pillar and the substrate and extending from the first surface of the substrate toward the second surface;
and
a first doped region set, located beside the first gate dielectric layer and extending from the first surface of the substrate toward the second surface, wherein a first channel is provided in the substrate between the first gate dielectric layer and the first doped region set;
and
the second portion is embedded into the substrate and further comprises:
a second gate dielectric layer, located between a second sidewall of the buried gate pillar and the substrate and extending from the first surface of the substrate toward the second surface;
and
a second doped region set, located beside the second gate dielectric layer and extending from the first surface of the substrate toward the second surface, wherein a second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.

7 more elements

A complementary semiconductor device, comprising:

a first metal oxide semiconductor device having a first channel and a second channel of a first conductivity type and embedded in a substrate, wherein the first channel and the second channel are located in the substrate at sides of a first buried gate pillar and the first buried gate pillar extends from a first surface of the substrate toward a second surface opposite to the first surface;
a second metal oxide semiconductor device having a third channel and a fourth channel of a second conductivity type and embedded in the substrate, wherein the third channel and the fourth channel are located in the substrate at sides of the second buried gate pillar and the second buried gate pillar extends from the first surface of the substrate toward the second surface.

Dependencies are inferred from the claim text.

Facts

Application: 15/054,134Filed 26 Feb 2016
Published: 31 Aug 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 62/235
Of FETs: of igfets
H10D 64/513
Disposition of the gate electrodes, e.g. buried gates: within recesses in the substrate, e.g. trench gates, groove gates or buried gates
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels