Method for fabricating a fin field effect transistor and a shallow trench isolation

A method for fabricating a shallow trench isolation (STI) structure, comprising:

• depositing a flowable dielectric layer in a trench of a substrate by introducing a silane-base precursor having a volumetric flowrate of 500 sccm to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 sccm to 600 sccm, the silane-base precursor and the nitrogen-base precursor being mixed under a first pressure ranging from 0.5 torr to 1.5 torr at a first temperature ranging from 30 centigrade to 105 centigrade;
• discontinuing supply of the silane-base precursor and the nitrogen-base precursor;
• and
• curing the flowable dielectric layer by introducing ozone gas and oxygen gas mixed under a second pressure ranging from 300 torr to 650 torr at a second temperature ranging from 50 centigrade to 250 centigrade, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1.

A method for fabricating a fin field effect transistor (FinFET), comprising:

• patterning a substrate to form trenches in the substrate and semiconductor fins between the trenches;
• introducing a silane-base precursor having a volumetric flowrate of 500 sccm to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 sccm to 600 sccm, the silane-base precursor and the nitrogen-base precursor being mixed under a first pressure ranging from 0.5 torr to 1.5 torr at a first temperature ranging from 30 centigrade to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate;
• introducing ozone gas and oxygen gas mixed under a second pressure ranging from 300 torr to 650 torr at a second temperature ranging from 50 centigrade to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1 during the flowable dielectric layer is treated;
• partially removing the flowable dielectric layer to form a plurality of insulators;
• forming a gate stack over portions of the semiconductor fins and over portions of the insulators;
• and
• forming a strained material over portions of the semiconductor fins revealed by the gate stack.