Via self alignment and shorting improvement with airgap integration capacitance benefit

A method comprising:

• forming a first metallization level in a dielectric layer on an integrated circuit substrate, the first metallization level including a plurality of metal lines;
• replacing a portion of the dielectric layer with a sacrificial material;
• forming a mask on the sacrificial material;
• removing the sacrificial material through the mask;
• and
• coupling a second metallization level to the first metallization level.

An apparatus comprising:

• an integrated circuit substrate;
• a first metallization level on the substrate;
• a second metallization level;
• and
• a mask disposed between the first metallization level and the second metallization level, the mask comprising a dielectric material having a porosity select to allow mass transport therethrough,
• wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.