Test apparatus and semiconductor chip
AssigneeSK hynix Inc.
InventorJong Ho JUNG
Life of this patent
Estimating the term…
Abstract
A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. The test apparatus may include a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data. The turnaround delay detection value may be generated by detecting a time of from a point of time when write data including a read command as the reference data is output to a point of time when the read data is received.
Claims19
A test apparatus comprising:
- a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus;
- and
- a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data,
- wherein the turnaround delay detection value is generated by detecting a time of from a point of time when write data including a read command as the reference data is output to a point of time when the read data is received.
A test apparatus comprising:
- a tester configured to set a delay compensation time of read data by detecting a turnaround delay of from a first point of time when write data including a read command is output in a turnaround delay compensation mode to a second point of time when the read data received exteriorly from the test apparatus is received, generate delayed read data by delaying the read data by the delay compensation time in a normal test mode, and perform a test result determination operation by comparing the delayed read data with the write data as reference data.
A test apparatus for a semiconductor chip, the test apparatus comprising:
- a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus;
- and
- a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data,
- wherein the turnaround delay detection value is generated by detecting a time of from a point of time when write data including a read command as the reference data is output to the semiconductor chip to a point of time when the read data is input from the semiconductor chip.
Dependencies are inferred from the claim text.