Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of string units, including first and second string units in a first block, third and fourth string units in a second block, each of the string units including a plurality of serially connected memory cells between first and second select transistors, and first through fourth select gate lines. The first select gate line is commonly connected to gates of the first select transistors of the first and third string units. The second select gate line is commonly connected to gates of the first select transistors of the second and fourth string units. The third select gate line is commonly connected to gates of the second select transistors of the first and fourth string units. The fourth select gate line is commonly connected to gates of the second select transistors of the second string unit and another string unit.

Dependencies are inferred from the claim text.