Arrays of bit-cells

A device comprising:

• a plurality of bit-cells coupled as an array, wherein a bit-cell includes:
• a memory element, wherein the memory element is polarized;
• a first switch element coupled to the memory element at a node;
• and
• a second switch element coupled to the first switch element and the memory element at the node;
• wherein the plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node;
• and
• wherein the array includes a plurality of memory elements of alternating polarity between bit-cells.

A method of operating a plurality of bit-cells coupled as an array, a bit-cell including a node to join a memory element, a first switch element, and a second switch element, the method comprising:

• switching a first bit-cell's first switch element, wherein the first bit-cell's first switch element is coupled to the first bit-cell's memory element at the first bit-cell's node;
• switching a second bit-cell's second switch element, to establish a set current path along the first bit-cell's memory element through the first bit-cell's first switch element and the second bit-cell's second switch element, wherein the second bit-cell's second switch element is coupled to the first bit-cell's memory element at the second bit-cell's node;
• switching the second bit-cell's first switch element, wherein the second bit-cell's first switch element is coupled to the first bit-cell's memory element and the second bit-cell's second switch element at the second bit-cell's node;
• and
• switching the first bit-cell's second switch element, to establish a reset current path along the first bit-cell's memory element through the second bit-cell's first switch element and the first bit-cell's second switch element, wherein the first bit-cell's second switch element is coupled to the first bit-cell's first switch element and memory element at the first bit-cell's node.