Current sense amplifiers, memory devices and methods
AssigneeMicron Technology, Inc.
InventorsOnegyun Na, Jongtae Kwak, Seong-Hoon Lee, Hoon Choi
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Abstract
A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.
Claims20
An amplifier, comprising:
- a first transistor coupled between first and second nodes;
- a second transistor coupled between third and fourth nodes, a control gate of the first transistor being coupled to the third node and a control gate of the second transistor being coupled to the first node;
- a third transistor coupled between the first and third nodes and configured to form a current path between the first and third nodes responsive to a first signal;
- a first enable circuit coupled between a first power source node and the first node and between the first power source node and the third node, the first enable circuit configured to form a current path between the first power source node and the first node and between the first power source node and the third node responsive to a second signal different from the first signal;
- and
- a second enable circuit coupled between a second power source node and the second node and between the second power source node and the fourth node, the second enable circuit configured to form a current path between the second power source node and the second node and between the second power source node and the fourth node responsive to the second signal.
An amplifier, comprising:
- a first transistor coupled between first and second nodes;
- a second transistor coupled between third and fourth nodes, a control gate of the first transistor being coupled to the third node and a control gate of the second transistor being coupled to the first node;
- a first control circuit comprising a first pair of transistors coupled between the first and third nodes and configured to form a first current path between the first and third nodes responsive to a first signal;
- a second control circuit comprising a second pair of transistors coupled between the first and third nodes and configured to form a second current path between the first and third nodes responsive to a second signal;
- a first enable circuit coupled to the first node and the third node and configured to form a current path between a first power source node and the first node and between the first power source node and the third node;
- and
- a second enable circuit coupled to the first node and the third node and configured to form a current path between a second power source node and the first node and between the second power source node and the third node.
A method, comprising:
- at a first time:
- coupling a first node to a second node via a first pair of transistors of a first control circuit of an amplifier in response to a first signal;
- and
- coupling the first node to the second node via a second pair of transistors of a second control circuit of an amplifier in response to a second signal;
- at a second time, enabling first and second enable circuits to sense an input signal via a pair of cross-coupled transistors;
- and
- at third time, disabling the first and second control circuits in response to the first and second signals, respectively.
Dependencies are inferred from the claim text.