Non-volatile ferroelectric memory cells with multilevel operation
AssigneeSabic Global Technologies B.V.
InventorsJi Hoon Park, Husam N. Alshareef, Mohd A. Khan, Ihab N. Odeh
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AssigneeSabic Global Technologies B.V.
InventorsJi Hoon Park, Husam N. Alshareef, Mohd A. Khan, Ihab N. Odeh
Estimating the term…
Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.
A method for storing multiple bits of information in a multi-level ferroelectric memory cell, comprising:
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The apparatus of claim 20, in which the controller is configured to create a conduction path in the channel by applying the at least one write pulse to the memory cell based, at least in part, on the pulse duration of the at least one write pulse.
The apparatus of claim 20, in which the controller is configured to set a charge carrier level in the conduction channel by applying the at least one write pulse to the memory cell based, at least in part, on the pulse duration of the at least one write pulse.
The apparatus of claim 20, in which the controller is configured to receive at least two bits in the received bit pattern.
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The apparatus of claim 20, in which the ferroelectric layer comprises an organic ferroelectric.
The apparatus of claim 20, in which the memory cell is one memory cell of an array of memory cells.
The apparatus of claim 20, wherein the controller is further configured to perform the steps of:
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An apparatus, comprising:
Dependencies are inferred from the claim text.